公开(公告)号：US06460066B1

公开(公告)日：2002-10-01

申请号：US09309627

申请日：1999-05-11

Applicant: Lin-Chieh Chen ,  Cheng-Sheng Han ,  Chun-Yu Chao

Inventor： Lin-Chieh Chen ,  Cheng-Sheng Han ,  Chun-Yu Chao

IPC: G06F750

CPC classification number: G06F1/0328 ,  G06F7/5095 ,  G06F2207/3884

Abstract: A triggerable, pipelined 40-bit high speed accumulator includes trigger and continuous modes which can be operated at 50 MHz clock frequency. The high speed accumulator can be combined with static random access memory (SRAM) so as to be applied to digital frequency synthesizer, function generator and arbitrary waveform generator, etc. The high speed accumulator has two operation modes-trigger mode and continuous mode. Under trigger mode, the accumulator waits for a trigger signal to initiate its operation, while under continuous mode, the accumulator works without any trigger signal.

Abstract translation: 可触发的流水线40位高速累加器包括可以在50 MHz时钟频率下运行的触发和连续模式。 高速累加器可与静态随机存取存储器（SRAM）结合使用，适用于数字频率合成器，功能发生器和任意波形发生器等。高速蓄能器具有两种操作模式 - 触发模式和连续模式。 在触发模式下，累加器等待触发信号启动其运行，而在连续模式下，累加器工作时没有任何触发信号。

公开(公告)号：US20020094053A1

公开(公告)日：2002-07-18

申请号：US09765770

申请日：2001-01-18

Inventor： Stephen F. Blazo

IPC: G06F001/02 ,  H03D003/24

CPC classification number: G06F1/0328 ,  G06F2211/902 ,  H03L7/16

Abstract: A frequency dither technique is used for reducing spurs due to phase increment errors in a direct digital synthesizer output sinusoid. The spurs for a desired output frequency are calculated and, if the spurs fall within a phase locked loop bandwidth, a pair of phase increment values are used representing a pair of frequencies that average to the desired output frequency and the spurs of which fall outside the phase locked loop bandwidth.

Abstract translation: 频率抖动技术用于在直接数字合成器输出正弦波中减少由于相位增量误差引起的杂波。 计算出期望输出频率的杂散，并且如果杂散落入锁相环带宽内，则使用一对相位增量值来表示平均到期望输出频率的一对频率，并且其中的马刺落在 锁相环带宽。

公开(公告)号：US06333649B1

公开(公告)日：2001-12-25

申请号：US09652385

申请日：2000-08-31

Applicant: Christopher H. Dick ,  Frederic J. Harris

Inventor： Christopher H. Dick ,  Frederic J. Harris

IPC: H03B2100

CPC classification number: G06F1/0342 ,  G06F1/0328 ,  G06F1/0353 ,  G06F2211/902 ,  H03B21/02

Abstract: A circuit arrangement and method for direct digital synthesis (DDS). In various embodiments, the invention feeds forward the phase error introduced by a quantizer in a DDS system. The error is fed forward to adjust the sine and cosine values that are obtained based on output from the quantizer. Correction of the sine and cosine values based on the fed-forward error values results in a significant reduction in the effect of spectral artifacts.

Abstract translation: 一种用于直接数字合成（DDS）的电路装置和方法。 在各种实施例中，本发明提供了量化器在DDS系统中引入的相位误差。 向前馈送误差，以根据量化器的输出调整获得的正弦和余弦值。 基于前馈误差值校正正弦和余弦值导致光谱伪影的显着降低。

公开(公告)号：US5963607A

公开(公告)日：1999-10-05

申请号：US850343

申请日：1997-05-02

Applicant: Glenn M. Romano ,  Craig R. Consiglio ,  Edward G. Tracey

Inventor： Glenn M. Romano ,  Craig R. Consiglio ,  Edward G. Tracey

IPC: G06F1/03 ,  H03D3/24

CPC classification number: G06F1/0328

Abstract: A chirp direct digital synthesizer is formed with a phase and frequency tracker circuit to provide both enhanced resolution and reduced power consumption. The phase and frequency tracker circuit operates at a sub-synchronous clock rate and provides periodic phase and frequency correction data to the direct digital synthesizer. The phase and frequency tracker circuit is suitable for both continuous wave and chirp direct digital synthesizer operation.

Abstract translation: 啁啾直接数字合成器形成有相位和频率跟踪器电路，以提供增强的分辨率和降低的功耗。 相位和频率跟踪器电路以子同步时钟速率工作，并向直接数字合成器提供周期性的相位和频率校正数据。 相位和频率跟踪器电路适用于连续波和啁啾直接数字合成器操作。

公开(公告)号：US5726609A

公开(公告)日：1998-03-10

申请号：US737823

申请日：1996-11-20

Applicant: Jari Lindholm

Inventor： Jari Lindholm

IPC: G06F1/03 ,  H03K7/02 ,  H04L27/04

CPC classification number: H03K7/02 ,  G06F1/0328

Abstract: A method and an apparatus for forming a pulse amplitude modulated signal in association with digital modulation. In the method symbols to be transmitted are formed from bits of an incoming bit stream. In order to achieve an accurate timing even when a bit clock contains abundant jitter, sample values of a pre-low-pass-filtered waveform of a pulse to be transmitted, covering at least one symbol period, are stored in a memory, sample values are read from the memory at the rate of a constant-frequency clock signal (f.sub.c, 4.times.f.sub.c), and a sample value read from the memory is multiplied by a predetermined factor the value of which is formed as a response to the symbol being transmitted.

Abstract translation: PCT No.PCT / FI95 / 00268 Sec。 371日期1996年11月20日 102（e）1996年11月20日日期PCT提交1995年5月18日PCT公布。 公开号WO95 / 32550 日期：1995年11月30日一种用于与数字调制相关联地形成脉冲幅度调制信号的方法和装置。 在要发送的方法中，由输入比特流的比特形成符号。 为了即使当位时钟包含大量抖动也能实现准确的定时时，要覆盖至少一个符号周期的待发送的脉冲的低通滤波波形的采样值被存储在存储器中，采样值 以恒定频率时钟信号（fc，4xfc）的速率从存储器读取，并且从存储器读取的采样值乘以其值作为对正被发送的符号的响应形成的预定因子。

公开(公告)号：US5430764A

公开(公告)日：1995-07-04

申请号：US115464

申请日：1993-09-01

Applicant: William A. Chren, Jr.

Inventor： William A. Chren, Jr.

IPC: G06F1/03 ,  G06F1/035 ,  H03L7/08 ,  H04L27/20

CPC classification number: H03L7/08 ,  G06F1/0328 ,  G06F1/0353

Abstract: A direct digital frequency synthesizer employs residue number system based processors to generate output waveforms of desired frequencies. The frequency synthesizer includes a phase accumulator comprising a plurality of individual adders, each adding a predefined quantity to a digit of a frequency setting word in which the individual digits are residue digits of differing moduli. The outputs of the independent adders form a combined residue output word which is used to address a memory storing signal samples. In one embodiment of the invention, the memory is a dual port ROM storing samples of one-quarter of a sine wave and the dual port ROM is simultaneously addressed to read a selected sample and an associated sample corresponding to the magnitude of a sample of the sine wave advanced by 90.degree. from the first sample. A sample select logic circuit selects one of the outputs of the dual port memory on the basis of selected bits of the combined residue word and data bits stored in the ROM with the samples to select and determine the sign of the sample of the sine wave. In another embodiment of the invention, the memory comprises a plurality of independent memories, corresponding to the number of independent adders, each storing residue information and a residue processing array processes the residue data obtained from the independent memories and provides a residue encoded signal to a residue-to-analog converter which generates the desired analog output.

Abstract translation: 直接数字频率合成器采用基于残余数系统的处理器来产生所需频率的输出波形。 频率合成器包括相位累加器，该相位累加器包括多个单独的加法器，每个加法器将预定义的量添加到频率设定字的数字，其中各个数字是不同模数的残差数字。 独立加法器的输出形成组合残差输出字，用于寻址存储信号样本的存储器。 在本发明的一个实施例中，存储器是存储四分之一正弦波的样本的双端口ROM，并且双端口ROM被同时寻址以读取所选择的采样和对应于所选择的采样的幅度的相关联样本 正弦波从第一个样品提前90度。 样本选择逻辑电路基于组合残留字的选定位和存储在ROM中的数据位选择双端口存储器的输出之一，其中样本选择并确定正弦波样本的符号。 在本发明的另一个实施例中，存储器包括多个独立的存储器，对应于独立加法器的数量，每个独立的加法器存储残差信息，并且残差处理阵列处理从独立存储器获得的残差数据，并将残差编码的信号提供给 产生所需模拟输出的模数转换器。

公开(公告)号：US5408687A

公开(公告)日：1995-04-18

申请号：US997084

申请日：1992-12-29

Applicant: Toshiyuki Ooga

Inventor： Toshiyuki Ooga

IPC: H04B1/04 ,  G06F1/03 ,  H03B1/04 ,  H03B28/00 ,  H04B1/10 ,  H04B1/38 ,  H04B7/00 ,  H03L7/18 ,  H04B1/40

CPC classification number: G06F1/0328 ,  H03B28/00 ,  H03B2202/05

Abstract: A synthesizer for use in a transmitter/receiver effectively eliminates spurious signals contained in an output signal. The synthesizer has a direct digital synthesizer for producing an output signal having a frequency corresponding to oscillation frequency data, and a voltage-controlled variable bandpass filter to which the output signal from the direct digital synthesizer is supplied. The oscillation frequency data is also supplied to a ROM, from which control voltage data corresponding to the supplied oscillation frequency data is read. The control voltage data from the ROM is supplied to a D/A converter which applies a control voltage to the voltage-controlled variable bandpass filter. The center frequency of the passband of the voltage-controlled variable bandpass filter is controlled by the applied control voltage in conformity with the frequency of the output signal from the direct digital synthesizer. The output signal from the direct digital synthesizer passes through a narrow passband of the voltage-controlled variable bandpass filter, so that spurious signals are eliminated from the output signal from the direct digital synthesizer.

Abstract translation: 用于发射机/接收机的合成器有效地消除了输出信号中包含的杂散信号。 合成器具有用于产生具有与振荡频率数据相对应的频率的输出信号的直接数字合成器，以及供给来自直接数字合成器的输出信号的压控可变带通滤波器。 振荡频率数据也被提供给ROM，读取对应于所提供的振荡频率数据的控制电压数据。 来自ROM的控制电压数据被提供给向压控可变带通滤波器施加控制电压的D / A转换器。 电压可控带通滤波器的通带的中心频率由施加的控制电压控制，与直接数字合成器的输出信号的频率一致。 来自直接数字合成器的输出信号通过压控可变带通滤波器的窄通带，从而从直接数字合成器的输出信号中消除杂散信号。

公开(公告)号：US5339338A

公开(公告)日：1994-08-16

申请号：US957223

申请日：1992-10-06

Applicant: Paul M. Elliott

Inventor： Paul M. Elliott

IPC: G06F1/03 ,  G06F5/10 ,  H04J3/06 ,  H04L7/00

CPC classification number: G06F5/10 ,  G06F1/0328 ,  H04J3/0626 ,  G06F2101/04 ,  G06F2205/061

Abstract: Apparatus and a method desynchronizes data by providing a high resolution FIFO depth measurement. A numerically controlled oscillator is combined with a FIFO memory to implement a variable frequency transmit clock signal having virtually unlimited frequency and phase resolution.

Abstract translation: 设备和方法通过提供高分辨率FIFO深度测量来同步数据。 数字振荡器与FIFO存储器组合以实现具有实际上无限频率和相位分辨率的可变频率发射时钟信号。

公开(公告)号：US5081297A

公开(公告)日：1992-01-14

申请号：US321187

申请日：1989-03-09

Applicant: Joseph A. Lebel ,  Charles D. Albrecht ,  Kar Kui Mark ,  Michael Ugenti

Inventor： Joseph A. Lebel ,  Charles D. Albrecht ,  Kar Kui Mark ,  Michael Ugenti

IPC: G01R31/319 ,  G06F1/03 ,  G06F1/14 ,  G06F13/38

CPC classification number: G06F1/0328 ,  G01R31/31919 ,  G01R31/31922 ,  G06F1/14 ,  G06F13/38

Abstract: A reconfigurable signal processing device that includes a plurality of programmable modules that are reconfigurable to perform one of a plurality of selected signal processing functions. The modules may be reconfigured under software control to act as one of a time base generator, a counter, an accumulator, an address register, a delay circuit, and a timer. The plurality of modules are selectively reconfigured and selectably interconnected by a configuration and control circuit that receives command signals from the host processor containing the control software. The device further includes a plurality of input channels for receiving and initially processing analog signals to be tested and a high speed memory for storing data as required for the selected signal processing device. The devices that can be formed by configuring and interconnecting the programmable modules are for example, a counter/timer, an arbitrary function generator, a pluse generator, and a digitizer.

Abstract translation: 一种可重新配置的信号处理设备，包括可重构以执行多个选择的信号处理功能之一的多个可编程模块。 模块可以在软件控制下重新配置，以充当时基发生器，计数器，累加器，地址寄存器，延迟电路和定时器之一。 多个模块通过从包含控制软件的主处理器接收命令信号的配置和控制电路选择性地重新配置和可选地互连。 该装置还包括用于接收和初始处理待测试的模拟信号的多个输入通道和用于存储所选信号处理装置所需的数据的高速存储器。 可以通过配置和互连可编程模块形成的装置例如是计数器/计时器，任意功能发生器，脉冲发生器和数字转换器。

公开(公告)号：US5031131A

公开(公告)日：1991-07-09

申请号：US593373

申请日：1990-10-01

Applicant: Jerome J. Mikos

Inventor： Jerome J. Mikos

IPC: G06F1/03

CPC classification number: G06F1/0328

Abstract: An improved digital data synthesizer has a phase accumulator into which adjustable step increments are clocked. The output of the phase accumulator is connected to address a memory, in which a waveform function is digitally stored. Samples read from the memory at the successive addresses are converted to analog form and filtered to produce a final output signal of a desired frequency. Register stages of the phase accumulator are pipelined to increase their speed. The synthesizer has a plurality of digital-to-analog converters, all on a single chip to equalize the delay times occurring within them. A lookup memory permits a variety of output waveforms to be generated. Several lookup tables for the same waveform are stored with different phase spacing between addresses, and a decoder/addresser automatically selects the lookup table that has been found to result in best performance for a particular frequency. One or more correction lookup table can also be provided. The outputs of the main table and the correction table are combined to produce an analog signal of reduced distortion.

Abstract translation: 改进的数字数据合成器具有相位累加器，可调节的步进增量被计时。 相位累加器的输出被连接到寻址数字存储波形函数的存储器。 在连续地址处从存储器读取的样本被转换为模拟形式并被滤波以产生期望频率的最终输出信号。 相位累加器的寄存器级流水线以提高其速度。 合成器具有多个数模转换器，全部在单个芯片上以均衡其内发生的延迟时间。 查找存储器允许生成各种输出波形。 相同波形的几个查找表在地址之间以不同的相位间隔存储，并且解码器/寻址器自动选择已经发现的查找表以导致特定频率的最佳性能。 还可以提供一个或多个校正查找表。 主表和校正表的输出被组合以产生具有减小的失真的模拟信号。