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公开(公告)号：US06886123B1
公开(公告)日：2005-04-26
申请号：US09656550
申请日：2000-09-06
CPC分类号： G01R31/3016
摘要： An arithmetic circuit for use with an RNS is provided. The arithmetic circuit includes an arithmetic core, test circuitry, and logic circuitry. The arithmetic core performs an RNS arithmetic operation, and the test circuitry verifies proper circuit delay by inducing oscillation at the output of the arithmetic core during testing. The logic circuitry produces a pass/fail signal based on whether the oscillation frequency of the arithmetic core is at least equal to a minimum threshold value. In one preferred embodiment, the logic circuitry includes a counter that counts oscillations of the output of the arithmetic core during testing, and a comparator that compares the output of the counter after a predetermined test period with the minimum threshold value. Also provided is a method for testing the propagation delay of an RNS arithmetic circuit having an arithmetic core.
摘要翻译： 提供了一种与RNS一起使用的运算电路。 运算电路包括运算核心，测试电路和逻辑电路。 算术核心执行RNS算术运算，并且测试电路通过在测试期间在算术核心的输出处引起振荡来验证适当的电路延迟。 逻辑电路基于算术核心的振荡频率是否至少等于最小阈值产生通过/失败信号。 在一个优选实施例中，逻辑电路包括计数器，该计数器在测试期间对运算核心的输出进行计数振荡;以及比较器，其将预定测试周期之后的计数器的输出与最小阈值进行比较。 还提供了一种用于测试具有算术核心的RNS运算电路的传播延迟的方法。
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公开(公告)号：US07165085B2
公开(公告)日：2007-01-16
申请号：US11106109
申请日：2005-04-14
IPC分类号： G06F7/38
摘要： A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.
摘要翻译： 模R加法器和用于RNS的模m，i，j比例缩放单元。 该加法器包括一个模数转换器，以及耦合到桶形移位器以存储桶形移位器的输出的动态存储单元。 在优选实施例中，动态存储单元包括用于桶形移位器的每个输出线的一个动态锁存器，每个动态锁存器包括与逆变器级联的时钟反相器。 一个模数m i，j个缩放单元包括执行残差转换和算术运算两者的修改后的模数移位器。 在不使用组合逻辑的情况下执行残余转换。 在一个优选实施例中，经修改的桶形移位器通过复制正常列的所有模m i / / SUB来执行残余转换 >输入线，它们是等同的模m m。 另一个模数转换单元包括基于桶形移位器的运算电路，以及耦合到运算电路以存储运算电路的输出的动态存储单元。
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公开(公告)号：US06898613B1
公开(公告)日：2005-05-24
申请号：US09383478
申请日：1999-08-26
摘要： A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.
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公开(公告)号：US06959315B2
公开(公告)日：2005-10-25
申请号：US10033992
申请日：2001-12-27
CPC分类号： G06F7/729 , G06F7/00 , G06F2207/3884 , H03M7/18
摘要： A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.
摘要翻译： 提供自定时数据处理电路模块。 将数据与Req握手输入一起提供给数据处理电路。 数据处理电路具有所有数据输入的同步处理延迟。 具有同步处理延迟的数据处理电路的示例是一个热残余系统算术处理电路。 数据处理电路处理输入数据，同时Req输入通过具有与数据处理电路基本相同的处理延迟的延迟电路传播。 因此，Req信号的传播延迟基本上等于数据处理电路的处理时间。 这允许延迟电路的输出用于锁存数据处理电路的输出并提供“数据就绪”输出。
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公开(公告)号：US5430764A
公开(公告)日：1995-07-04
申请号：US115464
申请日：1993-09-01
CPC分类号： H03L7/08 , G06F1/0328 , G06F1/0353
摘要： A direct digital frequency synthesizer employs residue number system based processors to generate output waveforms of desired frequencies. The frequency synthesizer includes a phase accumulator comprising a plurality of individual adders, each adding a predefined quantity to a digit of a frequency setting word in which the individual digits are residue digits of differing moduli. The outputs of the independent adders form a combined residue output word which is used to address a memory storing signal samples. In one embodiment of the invention, the memory is a dual port ROM storing samples of one-quarter of a sine wave and the dual port ROM is simultaneously addressed to read a selected sample and an associated sample corresponding to the magnitude of a sample of the sine wave advanced by 90.degree. from the first sample. A sample select logic circuit selects one of the outputs of the dual port memory on the basis of selected bits of the combined residue word and data bits stored in the ROM with the samples to select and determine the sign of the sample of the sine wave. In another embodiment of the invention, the memory comprises a plurality of independent memories, corresponding to the number of independent adders, each storing residue information and a residue processing array processes the residue data obtained from the independent memories and provides a residue encoded signal to a residue-to-analog converter which generates the desired analog output.
摘要翻译： 直接数字频率合成器采用基于残余数系统的处理器来产生所需频率的输出波形。 频率合成器包括相位累加器，该相位累加器包括多个单独的加法器，每个加法器将预定义的量添加到频率设定字的数字，其中各个数字是不同模数的残差数字。 独立加法器的输出形成组合残差输出字，用于寻址存储信号样本的存储器。 在本发明的一个实施例中，存储器是存储四分之一正弦波的样本的双端口ROM，并且双端口ROM被同时寻址以读取所选择的采样和对应于所选择的采样的幅度的相关联样本 正弦波从第一个样品提前90度。 样本选择逻辑电路基于组合残留字的选定位和存储在ROM中的数据位选择双端口存储器的输出之一，其中样本选择并确定正弦波样本的符号。 在本发明的另一个实施例中，存储器包括多个独立的存储器，对应于独立加法器的数量，每个独立的加法器存储残差信息，并且残差处理阵列处理从独立存储器获得的残差数据，并将残差编码的信号提供给 产生所需模拟输出的模数转换器。
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