公开(公告)号：US07464129B2

公开(公告)日：2008-12-09

申请号：US10291859

申请日：2002-11-08

Applicant: Tariq Kurd

Inventor： Tariq Kurd

IPC: G06F7/38

CPC classification number: G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

Abstract: The invention provides circuitry for carrying out a square root operation. The circuitry utilizes iteration circuitry for carrying out a plurality of iterations. The iteration circuitry includes a circuit for calculating a root multiple, the root multiple being a multiple of a current quotient value. The root multiple is used by the iteration circuitry to modify a current remainder.

Abstract translation: 本发明提供了用于执行平方根操作的电路。 电路利用迭代电路进行多次迭代。 迭代电路包括用于计算根倍数的电路，根倍数是当前商值的倍数。 根倍数由迭代电路用于修改当前的余数。

公开(公告)号：US20080250228A1

公开(公告)日：2008-10-09

申请号：US12082046

申请日：2008-04-07

Applicant: Paul Elliott ,  Tariq Kurd

Inventor： Paul Elliott ,  Tariq Kurd

IPC: G06F9/312

CPC classification number: G06F12/1441 ,  G06F12/145 ,  G06F12/1483

Abstract: A semiconductor integrated circuit includes a hardware mechanism arranged to ensure that associations between instructions and data are enforced so that a processor cannot fetch data from an instruction that is not authorised to do so. A Memory Protection Unit stores entries comprising instructions and associated data memory ranges. A hardware arrangement impairs the operation of the circuit if the CPU attempts to make a data fetch from an instruction that is outside the range associated with data in a Memory Protection Unit. Such functioning may be by issuing a chip reset. The Memory Protection Unit may be implemented in a Memory Management Unit having an extension so as to store a validity flag. The validity flag may only be set by a secure process such as the CPU well entrusted code or by a separate trusted hardware source. In this way, an operating system may function as normal referring to the Memory Management Unit as necessary, but security may be enforced through hardware.

Abstract translation: 半导体集成电路包括硬件机制，其被配置为确保指令和数据之间的关联被强制执行，使得处理器不能从未被授权的指令获取数据。 存储器保护单元存储包括指令和相关数据存储器范围的条目。 如果CPU尝试从与存储器保护单元中的数据相关联的范围之外的指令进行数据取出，那么硬件安排会影响电路的操作。 这种功能可能是通过发出芯片复位。 存储器保护单元可以在具有扩展的存储器管理单元中实现，以便存储有效性标志。 有效性标志只能通过诸如CPU良好委托的代码或单独的可信硬件源之类的安全处理来设置。 以这种方式，操作系统可以根据需要正常地参考存储器管理单元，但是可以通过硬件来执行安全性。

公开(公告)号：US07411441B2

公开(公告)日：2008-08-12

申请号：US10896371

申请日：2004-07-21

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: G05F1/10

CPC classification number: G05F3/265 ,  G05F3/205

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract translation: 一种偏置电路，包括具有控制端子的第一开关器件，以及第一和第二开关端子。 第一开关端子连接到电源电压，第二开关端子通过第一电阻元件连接到地，并且控制端子由根据电路的操作模式确定的参考电压提供。 电路还包括连接在控制端和地之间的第一分支，包括与第二开关装置串联的第二电阻元件。 形成第一电流镜的一部分的第二开关器件具有用于产生所产生的偏置值的第二支路。 在正常工作模式下，参考电压取决于产生的偏置值，而在待机工作模式下，参考电压连接到低电位。

公开(公告)号：US07395296B2

公开(公告)日：2008-07-01

申请号：US10291861

申请日：2002-11-08

Applicant: Tariq Kurd

Inventor： Tariq Kurd

IPC: G06F7/38

CPC classification number: G06F7/026 ,  G06F7/483

Abstract: Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second part is arranged to identify at least one characteristic of the at least one number and to provide an output and correction circuitry for providing, if necessary, a correct result in dependence on the output of the second part, wherein said first and second parts are arranged to operate in parallel.

Abstract translation: 提供电路用于相对于至少一个数字执行非算术运算。 电路包括用于相对于至少一个数字执行非算术运算的第一部分，第一部分提供结果。 第二部分被布置成识别至少一个数字的至少一个特征，并且提供输出和校正电路，用于根据第二部分的输出提供必要的正确结果，其中所述第一和第二部分 被布置成并行操作。

公开(公告)号：US07383481B2

公开(公告)日：2008-06-03

申请号：US11101167

申请日：2005-04-07

Applicant: Robert Warren ,  Robert M. Mills

Inventor： Robert Warren ,  Robert M. Mills

IPC: G01R31/28

CPC classification number: G01R31/318552

Abstract: An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. The test circuitry is arranged to use the clock signal for testing the functional circuitry.

Abstract translation: 包括功能电路的集成电路; 连接到所述功能电路的测试电路，其中所述测试电路被布置成控制所述功能电路的测试; 以及连接到功能电路和测试电路两者的时钟信号发生电路。 测试电路被设置为使用时钟信号来测试功能电路。

公开(公告)号：US20080123748A1

公开(公告)日：2008-05-29

申请号：US12020668

申请日：2008-01-28

Applicant: Martin Bolton

Inventor： Martin Bolton

IPC: H04N7/26 ,  H04N7/32

CPC classification number: H04N19/42 ,  H04N19/126 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61 ,  H04N19/91

Abstract: Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

Abstract translation: 数据是离散余弦变换并流式传输到产生量化和反量化块的处理器。 第二流数据连接将反量化块流向逆离散余弦变换块，以产生重建的预测误差宏块。 加法电路将每个重建的预测误差宏块及其对应的预测器宏块相加以生成相应的重建宏块。 量化的宏块是锯齿形扫描，运行级编码和可变长度编码以生成和编码比特流。

公开(公告)号：US07346822B2

公开(公告)日：2008-03-18

申请号：US11101377

申请日：2005-04-07

Applicant: Robert Warren ,  Robert M. Mills

Inventor： Robert Warren ,  Robert M. Mills

IPC: G01R31/28

CPC classification number: G01R31/318552

Abstract: An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

Abstract translation: 包括测试电路的集成电路，测试电路包括用于计数时钟信号并具有用于提供控制信号的输出的计数器。 计数器被布置成具有内部状态，并且计数器被布置成在计数器的内部状态上改变控制信号达到预定值。

公开(公告)号：US20080030172A1

公开(公告)日：2008-02-07

申请号：US11829760

申请日：2007-07-27

Applicant: Saul Darzy

Inventor： Saul Darzy

IPC: H02J7/00

CPC classification number: H02J7/0029

Abstract: A battery charger is provided which has a power output to charge a battery. The battery charger comprises a power input and a circuit for determining a temperature at the battery charger. The battery charger further includes a controller which varies the power output among a plurality of non-zero power levels in dependence upon the difference between the determined temperature and a reference temperature.

Abstract translation: 提供电池充电器，其具有对电池充电的功率输出。 电池充电器包括电源输入和用于确定电池充电器温度的电路。 电池充电器还包括控制器，其根据所确定的温度和参考温度之间的差异，在多个非零功率电平之间改变功率输出。

公开(公告)号：US20070262653A1

公开(公告)日：2007-11-15

申请号：US11682230

申请日：2007-03-05

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/00

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 该类型的集成电路包括可用作发起者和目标的多个单元。 至少一些单元是用于电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的互连连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。

公开(公告)号：US20070180464A1

公开(公告)日：2007-08-02

申请号：US11461306

申请日：2006-07-31

Applicant: Andrew Dellow ,  Peter Bennett

Inventor： Andrew Dellow ,  Peter Bennett

IPC: H04N7/173 ,  H04N7/16 ,  G06F17/50 ,  H04N7/167

CPC classification number: H04N7/1675 ,  H04L9/0891 ,  H04L9/3247 ,  H04L2209/56 ,  H04L2209/601 ,  H04N21/4181 ,  H04N21/43607 ,  H04N21/4405 ,  H04N21/8166

Abstract: An integrated circuit restricts use of a data item and includes a data memory storing the data item; a value memory storing a value; a signature input that receives a signature derived from data in a data item field and a value in a value field, the signature being in a coded form; a decoding circuit that decodes the signature and outputs information representing the data in the data item field and the value in the value field; and a comparison circuit that receives the decoding circuit output, determines whether the information representing the data from the data item field corresponds to the stored data item and whether the information representing the value from the value field corresponds to the value stored in the value memory, and outputs a comparison signal according to the determinations. The circuit restricts the use of the data item according to the comparison signal.

Abstract translation: 集成电路限制数据项的使用，并且包括存储数据项的数据存储器; 存储值的值存储器; 签名输入，其接收从数据项字段中的数据和值字段中的值导出的签名，所述签名处于编码形式; 解码电路，对所述签名进行解码并输出表示所述数据项字段中的数据的信息和所述值字段中的值; 以及接收解码电路输出的比较电路，确定表示来自数据项字段的数据的信息是否对应于所存储的数据项，以及表示来自值字段的值的信息是否对应于存储在值存储器中的值， 并根据确定输出比较信号。 电路根据比较信号限制数据项的使用。