公开(公告)号：US07065601B2

公开(公告)日：2006-06-20

申请号：US10456860

申请日：2003-06-06

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/14

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

公开(公告)号：US20050015565A1

公开(公告)日：2005-01-20

申请号：US10621012

申请日：2003-07-15

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0292

Abstract: A prototype system is described having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract translation: 描述了一种具有包括片上处理器和通过接口连接到片外资源的片上路由器的集成电路的原型系统。 芯片上的请求引导单元接收存储器访问请求，并根据两个地址映射中的任一个引导它们。 在一个地址映射中，将第一范围的地址分配给至少一个片上资源，并且将第二范围的地址分配给该接口。 在另一个存储器地址映射中，第一个地址范围也被分配给接口。 还描述了包括这种请求引导单元的集成电路以及用于评估原型系统的方法。

公开(公告)号：US07774574B2

公开(公告)日：2010-08-10

申请号：US10621012

申请日：2003-07-15

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F12/06

CPC classification number: G06F12/0292

Abstract: A prototype system having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract translation: 具有集成电路的原型系统，该集成电路包括片上处理器和通过接口连接到片外资源的片上路由器。 芯片上的请求引导单元接收存储器访问请求，并根据两个地址映射中的任一个引导它们。 在一个地址映射中，将第一范围的地址分配给至少一个片上资源，并且将第二范围的地址分配给该接口。 在另一个存储器地址映射中，第一个地址范围也被分配给接口。 还描述了包括这种请求引导单元的集成电路以及用于评估原型系统的方法。

公开(公告)号：US20070283140A1

公开(公告)日：2007-12-06

申请号：US11787227

申请日：2007-04-13

Applicant: Andrew Jones ,  Stuart Ryan

Inventor： Andrew Jones ,  Stuart Ryan

IPC: G06F12/14 ,  G06F9/24

CPC classification number: G06F9/4403 ,  G06F21/575 ,  G06F2221/2105

Abstract: An integrated circuit is operable to execute boot loader code and a boot code from external memory. To provide security so that the CPU does not execute malicious codes, the circuit resets in a restricted mode in which only certain functional units may be connected. In the restricted mode the CPU is only able to fetch boot code from an external memory for transfer to an internal memory. A hash function operates on the fetched boot code to determine whether it is authentic and, if it is determined that the code is authentic the circuit is reset to an unrestricted mode to continue executing from the boot code now stored in the internal memory. Further security is provided by a watchdog timer function which resets the circuit if the boot code is not determined to be authentic within a threshold period of time.

Abstract translation: 集成电路可操作以从外部存储器执行引导加载器代码和引导代码。 为了提供安全性以使CPU不执行恶意代码，该电路在仅可以连接某些功能单元的限制模式下复位。 在限制模式下，CPU只能从外部存储器获取引导代码，以传输到内部存储器。 哈希函数对获取的引导代码进行操作以确定其是否是真实的，并且如果确定代码是可信的，则电路被重置为不受限制的模式以从现在存储在内部存储器中的引导代码继续执行。 看门狗定时器功能还提供进一步的安全性，如果在阈值时间段内引导代码未被确定为可靠的，则复位电路。

公开(公告)号：US20060195645A1

公开(公告)日：2006-08-31

申请号：US11415265

申请日：2006-05-01

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/24

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract translation: 描述了具有至少一个芯片侧端口的接口，该芯片侧端口具有用于传送分组的场的第一多个引脚，以及第一和第二电路侧端口，每个端口具有一组具有比第一组引脚小的引脚的引脚 芯片侧端口。 该接口被构造成使得来自片外电路的中断信号可以以片上的方式传送，使得中断信号与从连接到片上通信路径的片上模块接收到的中断信号无法区分。 同样的原理适用于掉电信号。

公开(公告)号：US20050005226A1

公开(公告)日：2005-01-06

申请号：US10456860

申请日：2003-06-06

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/24 ,  G06F13/38 ,  G06F17/50 ,  H03M13/00

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract translation: 描述了具有至少一个芯片侧端口的接口，该芯片侧端口具有用于传送分组的场的第一多个引脚，以及第一和第二电路侧端口，每个端口具有一组具有比第一组引脚小的引脚的引脚 芯片侧端口。 该接口被构造成使得来自片外电路的中断信号可以以片上的方式传送，使得中断信号与从连接到片上通信路径的片上模块接收到的中断信号不可区分。 同样的原理适用于掉电信号。

公开(公告)号：US08260994B2

公开(公告)日：2012-09-04

申请号：US11415265

申请日：2006-05-01

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/24 ,  G06F13/36

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract translation: 描述了具有至少一个芯片侧端口的接口，该芯片侧端口具有用于传送分组的场的第一多个引脚，以及第一和第二电路侧端口，每个端口具有一组具有比第一组引脚小的引脚的引脚 芯片侧端口。 该接口被构造成使得来自片外电路的中断信号可以以片上的方式传送，使得中断信号与从连接到片上通信路径的片上模块接收到的中断信号无法区分。 同样的原理适用于掉电信号。

公开(公告)号：US20070262653A1

公开(公告)日：2007-11-15

申请号：US11682230

申请日：2007-03-05

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/00

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 该类型的集成电路包括可用作发起者和目标的多个单元。 至少一些单元是用于电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的互连连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。

公开(公告)号：US09367517B2

公开(公告)日：2016-06-14

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F15/78 ,  H04L12/933

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。

公开(公告)号：US09058283B2

公开(公告)日：2015-06-16

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。