公开(公告)号：US20140229682A1

公开(公告)日：2014-08-14

申请号：US13765813

申请日：2013-02-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.

Abstract translation: 一种类型的条件概率提取器通过维护与从第二存储器提取的一组存储器元件中的存储器元件有关的信息，从另一存储器预取诸如用于高速缓存的数据。 信息可以是已经为组中的不同存储器段获取的存储器元素的总数。 该信息是响应于从一组存储器元件中的存储器元件的段中提取一个或多个存储器元件来保持的。 当与存储元件组中的存储元件相关的信息指示已经满足预取条件时，将存储器元件的特定段中的一个或多个剩余存储元件从第二存储器预取到第一存储器中。

公开(公告)号：US20140223445A1

公开(公告)日：2014-08-07

申请号：US13761985

申请日：2013-02-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。

公开(公告)号：US20140181428A1

公开(公告)日：2014-06-26

申请号：US13726144

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa R. Hsu ,  Gabriel H. Loh ,  Bradford M. Beckmann ,  Michael Ignatowski

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware.

Abstract translation: 堆叠堆叠的存储器件实现集成的QoS管理器以提供集中的QoS功能，以促进一个或多个指定的QoS目标，以便由处理系统的其他组件共享存储器资源。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一个或多个逻辑管芯。 逻辑模块为存储器控制器和QoS管理器实现硬件逻辑。 存储器控制器可耦合到一个或多个堆叠的存储器管芯组的外部的一个或多个器件，并且操作以从一个或多个外部器件服务存储器访问请求。 QoS管理器包括用于执行可由操作系统，管理程序，作业管理软件或正在执行的其他应用或经由硬编码逻辑或固件指定的一个或多个QoS目标的操作的逻辑。

公开(公告)号：US20140181389A1

公开(公告)日：2014-06-26

申请号：US13724867

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  Y02D10/13

Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.

Abstract translation: 提供数据缓存方法和系统。 数据高速缓存方法将数据加载到安装高速缓存和高速缓存（同时或连续）中，并在数据尚未完全加载到高速缓存中时从安装高速缓存返回数据。 数据缓存系统包括处理器，耦合到处理器的存储器，耦合到处理器和存储器的高速缓存以及耦合到处理器和存储器的安装高速缓存。 该系统被配置为当数据尚未完全加载到高速缓存中时，将数据从存储器加载到安装高速缓存和高速缓存（同时或串行）中，并将数据从安装高速缓存返回到处理器。

公开(公告)号：US20140089609A1

公开(公告)日：2014-03-27

申请号：US13627895

申请日：2012-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel ,  Gabriel H. Loh

IPC: H01L23/535 ,  G06F12/00 ,  H01L21/768

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system is provided that includes an interposer having memory controller circuitry embedded therein. The interposer includes conductive vias that are embedded within and that extend through the interposer. The memory controller circuitry can be coupled to some of the conductive vias. In some implementations, other ones of the conductive vias are configured to be coupled to a processor and a memory module that can be mounted along a surface of the interposer. Conductive links are disposed on a surface of the interposer to couple the processor and the memory module to the memory controller circuitry.

Abstract translation: 提供了一种系统，其包括嵌入其中的存储器控​​制器电路的插入器。 插入器包括嵌入在插入件内并延伸穿过插入件的导电通孔。 存储器控制器电路可以耦合到一些导电通孔。 在一些实施方案中，导电通孔中的其它导电通孔被配置为耦合到处理器和可沿着插入器的表面安装的存储器模块。 导电链路设置在插入器的表面上，以将处理器和存储器模块耦合到存储器控制器电路。