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151.发明授权公开(公告)号：US12040928B2
公开(公告)日：2024-07-16
申请号：US18298498
申请日：2023-04-11
Inventor： Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04L27/26 , H04J11/00 , H04L1/00 , H04L7/08 , H04L65/611
CPC classification number: H04L27/2627 , H04J11/004 , H04L1/0041 , H04L1/0058 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L7/08 , H04L27/26 , H04L27/2613 , H04L27/2647 , H04L65/611
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US11764808B2
公开(公告)日：2023-09-19
申请号：US17577280
申请日：2022-01-17
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/1105 , H03M13/255 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0071 , H04L27/3422 , H04L1/0057
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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公开(公告)号：US11750224B2
公开(公告)日：2023-09-05
申请号：US17165625
申请日：2021-02-02
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/036 , H03M13/116 , H03M13/1148 , H03M13/1165 , H03M13/255 , H03M13/616 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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154.发明授权公开(公告)号：US11736123B2
公开(公告)日：2023-08-22
申请号：US17891189
申请日：2022-08-19
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
IPC: G06F11/00 , H03M13/00 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , G06T7/162 , H03M13/15 , H04W72/044
CPC classification number: H03M13/1148 , H03M13/1105 , H03M13/1165 , H03M13/255 , H03M13/27 , H03M13/2778 , H03M13/2906 , H03M13/618 , H03M13/6362 , G06T7/162 , H03M13/1102 , H03M13/1111 , H03M13/152 , H04W72/0466
Abstract: A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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155.发明授权公开(公告)号：US11695492B2
公开(公告)日：2023-07-04
申请号：US17499192
申请日：2021-10-12
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
IPC: H04W4/00 , H04J13/10 , H04B1/7073 , H04L1/00 , H04L27/26
CPC classification number: H04J13/10 , H04B1/7073 , H04L1/0041 , H04L1/0048 , H04L1/0071 , H04L1/0075 , H04L27/2605 , H04L27/2613 , H04L1/0065
Abstract: An apparatus for transmitting broadcasting signal using transmitter identification and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.
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Patent Agency Ranking
156.发明授权公开(公告)号：US11658858B2
公开(公告)日：2023-05-23
申请号：US17540301
申请日：2021-12-02
Inventor： Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04L27/26 , H04J11/00 , H04L1/00 , H04L7/08 , H04L65/611
CPC classification number: H04L27/2627 , H04J11/004 , H04L1/0041 , H04L1/0058 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L7/08 , H04L27/26 , H04L27/2613 , H04L27/2647 , H04L65/611
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US11611357B2
公开(公告)日：2023-03-21
申请号：US17240804
申请日：2021-04-26
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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158.发明授权公开(公告)号：US11588503B2
公开(公告)日：2023-02-21
申请号：US17315450
申请日：2021-05-10
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
Abstract: A parity puncturing apparatus and method for variable length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.
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公开(公告)号：US11588502B2
公开(公告)日：2023-02-21
申请号：US17386373
申请日：2021-07-27
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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公开(公告)号：US11563616B2
公开(公告)日：2023-01-24
申请号：US17153038
申请日：2021-01-20
Inventor： Jae-Young Lee , Sun-Hyoung Kwon , Sung-Ik Park , Bo-Mi Lim , Heung-Mook Kim
IPC: H04L27/26 , H03M13/35 , H03M13/11 , H04L1/00 , H03M13/25 , H03M13/27 , H03M13/29 , H04L5/00 , H03M13/15
Abstract: An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and the time interleaver performs the interleaving by using one of a plurality of operation modes.
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