公开(公告)号：US20080092018A1

公开(公告)日：2008-04-17

申请号：US11586101

申请日：2006-10-25

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2996 ,  H03M13/2993

摘要： Tail-biting turbo code for arbitrary number of information bits. A novel means is presented in which, for most cases, no extra symbols at all need to be padded to an input sequence to ensure that a turbo encoder operates according to tail-biting (i.e., where the beginning and ending state of the turbo encoder is the same). In a worst case scenario, only a single symbol (or a single bit) needs to be padded to the input sequence. Herein, all of the input bits of the input sequence are interleaved within the turbo encoding. In the instance where the at most one symbol (or at most one bit) needs to be padded to the input sequence, then that at most one symbol (or one bit) is also interleaved within the turbo encoding. Moreover, any size of an input sequence can be accommodated using the means herein to achieve tail-biting.

摘要翻译： 尾随Turbo码用于任意数量的信息位。 提出了一种新颖的方法，其中在大多数情况下，根本不需要将额外的符号填充到输入序列，以确保turbo编码器根据尾巴（即，其中turbo编码器的开始和结束状态 是一样的）。 在最坏的情况下，只需要将一个符号（或一个位）填充到输入序列中。 这里，输入序列的所有输入比特在Turbo编码中进行交织。 在最多一个符号（或最多一位）需要被填充到输入序列的情况下，那么在turbo编码中最多一个符号（或一个比特）也被交织。 此外，使用这里的手段可以适应任何大小的输入序列以实现尾巴咬合。

公开(公告)号：US08572469B2

公开(公告)日：2013-10-29

申请号：US12915936

申请日：2010-10-29

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： G06F11/1008 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3972

摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。 本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎 正则排列）交错。 选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。 此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。

公开(公告)号：US08386906B2

公开(公告)日：2013-02-26

申请号：US13424159

申请日：2012-03-19

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： G06F11/00

CPC分类号： H03M13/116 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6561

摘要： Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

摘要翻译： 多CSI（循环移位身份）基于子矩阵的LDPC（低密度奇偶校验）码。 使用包括至少一个双值条目并且还可以包括至少一个单值条目和/或至少一个全零值条目的CSI参数集合来生成LDPC矩阵。 单值条目中的一个可以是0（用于生成具有循环移位值0的CSI矩阵，对应于身份子矩阵，使得沿着对角线的所有条目具有元素值1，并且其中所有其他元素 是0）。 一旦生成了LDPC矩阵，就采用LDPC编码信号进行解码，对其中编码的信息比特进行估计。 此外，LDPC矩阵本身可以用作LDPC生成器矩阵（或者可替换地，LDPC生成器矩阵可以通过处理LDPC矩阵来生成）用于对信息比特进行编码。

公开(公告)号：US08341490B2

公开(公告)日：2012-12-25

申请号：US13429553

申请日：2012-03-26

申请人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/2739 ,  H03M13/6306 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1819

摘要： Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.

公开(公告)号：US08145974B2

公开(公告)日：2012-03-27

申请号：US12362543

申请日：2009-01-30

申请人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/2739 ,  H03M13/6306 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1819

摘要： Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.

摘要翻译： 用于速率匹配的虚拟限制缓冲区修改。 在通信设备内采用缩小尺寸的存储器模块以帮助存储根据turbo解码所采用的对数似然比（LLR）。 该架构也适用于除turbo码之外的其他类型的纠错码（ECC）。 选择存储器大小以匹配包含在传输内的编码比特数（例如，包括信息比特和冗余/奇偶校验比特）。 所接收的信号可以是根据混合自动重传请求（HARQ）传输而进行的各种传输。 当从第一HARQ传输计算的LLR不足以解码时，那些LLR被选择性地存储在存储器模块中。 当接收到对应于第二HARQ传输的LLR时，对应于第一HARQ传输和第二HARQ传输两者的LLR从存储器模块传递以用于解码。

公开(公告)号：US08074155B2

公开(公告)日：2011-12-06

申请号：US11830327

申请日：2007-07-30

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2739 ,  H03M13/2903 ,  H03M13/2996 ,  H03M13/3988 ,  H03M13/635 ,  H03M13/6362 ,  H03M13/6525

摘要： Tail-biting turbo coding to accommodate any information and/or interleaver block size. The beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

摘要翻译： 尾部涡轮编码以适应任何信息和/或交织器块大小。 turbo编码器的开始和结束状态可以使用非常少量的虚拟位相同。 在一些情况下，在经过交织之后和在通过通信信道传输turbo编码信号之前去除在进行交织之前添加到信息块的任何虚拟位，从而增加吞吐量（例如，这些虚拟位不是经由通信信道实际发送 ）。 在其他情况下，将伪比特添加到使用第一构成编码器编码的信息块以及使用第二构成编码器对交织的信息块进行编码。

公开(公告)号：US20110055663A1

公开(公告)日：2011-03-03

申请号：US12941178

申请日：2010-11-08

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2771 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0066

摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function that is based on an address mapping which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 提出了一种新颖的方法，其中使用基于对应于解码处理（＆pgr; -1）的交织逆顺序的地址映射的索引函数来采用预期地址生成。 根据并行turbo解码处理，代替通过从存储器单元顺序访问数据元素来执行自然次序相位解码处理，基于基于映射和交织（＆pgr）的索引函数来执行地址的访问。 ）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数还允许通过从存储体位置顺序地访问数据元素来进行交织（＆amp;）顺序相位解码处理。

公开(公告)号：US20110047436A1

公开(公告)日：2011-02-24

申请号：US12915936

申请日：2010-10-29

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： G06F11/1008 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3972

摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。 本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎 正则排列）交错。 选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。 此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。

公开(公告)号：US07716564B2

公开(公告)日：2010-05-11

申请号：US11860679

申请日：2007-09-25

申请人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/03

CPC分类号： H03M13/3955 ,  H03M13/4107 ,  H03M13/4146

摘要： Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

摘要翻译： 基数4 SOVA的注册交换网络（软输出维特比算法）。 两个网格级同时并行并行处理（例如，在单个时钟周期内），从而显着增加数据吞吐量。 REX（注册交换）模块中的任何一个或多个模块都使用基数4架构来实现，以增加数据吞吐量。 根据基数4解码处理的原理实现SMU（幸存者存储单元），PED（路径等价检测器）和RMU（可靠性测量单元）中的任何一个或多个。

公开(公告)号：US20100031125A1

公开(公告)日：2010-02-04

申请号：US11830327

申请日：2007-07-30

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/27 ,  G06F11/10

CPC分类号： H03M13/2739 ,  H03M13/2903 ,  H03M13/2996 ,  H03M13/3988 ,  H03M13/635 ,  H03M13/6362 ,  H03M13/6525

摘要： Tail-biting turbo coding to accommodate any information and/or interleaver block size. A means is presented by which the beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

摘要翻译： 尾部涡轮编码以适应任何信息和/或交织器块大小。 提出了一种可以使用极小数量的虚拟位使Turbo编码器的开始和结束状态相同的装置。 在一些情况下，在经过交织之后和在通过通信信道传输turbo编码信号之前去除在进行交织之前添加到信息块的任何虚拟位，从而增加吞吐量（例如，这些虚拟位不是经由通信信道实际发送 ）。 在其他情况下，将伪比特添加到使用第一构成编码器编码的信息块以及使用第二构成编码器对交织的信息块进行编码。