公开(公告)号：US09584157B2

公开(公告)日：2017-02-28

申请号：US14432859

申请日：2013-10-02

申请人： Panasonic Intellectual Property Corporation of America

发明人： Yutaka Murakami

IPC分类号： H03M13/00 ,  H03M13/03 ,  H03M13/11 ,  H03M13/23 ,  H03M13/39

CPC分类号： H03M13/1111 ,  G06F11/10 ,  H03M13/033 ,  H03M13/036 ,  H03M13/1105 ,  H03M13/1154 ,  H03M13/118 ,  H03M13/23 ,  H03M13/235 ,  H03M13/3988 ,  H03M13/611 ,  H03M13/616 ,  H03M13/617 ,  H04L1/0041 ,  H04L1/0058 ,  H04L1/0059

摘要： An encoding method of generating an encoded sequence by performing encoding of a given encoding rate based on a predetermined parity check matrix. The predetermined matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. A parity check polynomial satisfying zero of the LDPC convolutional code is expressible by using a specific mathematical expression.

摘要翻译： 一种通过基于预定奇偶校验矩阵执行给定编码率的编码来生成编码序列的编码方法。 预定矩阵是第一奇偶校验矩阵或第二奇偶校验矩阵。 第一奇偶校验矩阵对应于使用多个奇偶校验多项式的低密度奇偶校验（LDPC）卷积码，并且通过在第一奇偶校验上执行行排列和列置换中的至少一个来生成第二奇偶校验矩阵 矩阵。 通过使用特定的数学表达式可以表达满足LDPC卷积码的零的奇偶校验多项式。

公开(公告)号：US08898547B2

公开(公告)日：2014-11-25

申请号：US12463386

申请日：2009-05-09

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H03M13/00 ,  H03M13/39 ,  H03M13/29 ,  H03M13/25

CPC分类号： H03M13/3905 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/6362 ,  H03M13/6516

摘要： Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.

摘要翻译： 速率控制适应通信。 在通信系统（编码器和解码器）的两端采用通用网格，以不同速率对数据进行编码和解码。 编码采用单个编码器，其输出位可以被选择性地打孔以支持根据速率控制序列的多个调制（星座和映射）。 单个解码器可操作以解码编码器对数据进行编码的各种速率中的每一个。 速率控制序列可以包括在编码和解码期间重复的周期中布置的速率控制的数量。 编码器和解码器中的一个或两者可以基于包括通信系统的操作条件，信噪比（SNR）等的变化的各种操作参数自适应地选择新的速率控制序列。

公开(公告)号：US20080043856A1

公开(公告)日：2008-02-21

申请号：US11792712

申请日：2005-11-09

申请人： Seong-Chul Cho ,  Gweon-Do Jo ,  Hyung-Jin Kim ,  Jin-Up Kim ,  Sang-Woo Nam

发明人： Seong-Chul Cho ,  Gweon-Do Jo ,  Hyung-Jin Kim ,  Jin-Up Kim ,  Sang-Woo Nam

IPC分类号： H04L1/08

CPC分类号： H04L1/0041 ,  H03M13/2903 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0066

摘要： An encoding system using a non-binary turbo code and an encoding method thereof is capable of encoding an input signal at a low code rate and at once by spreading the input signal. An input information bit sequence is spread according to the obtained channel code rate and outputting the same in the form of one pair of input sequences, the pair of input sequences is encoded, and a parity bit sequence is generated and an encoded data sequence is generated by multiplexing the parity bit sequence.

摘要翻译： 使用非二进制turbo码的编码系统及其编码方法能够以低码率编码输入信号，并且通过扩展输入信号一次。 输入信息比特序列根据所获得的信道码率进行扩频，并以一对输入序列的形式输出，对该输入序列进行编码，生成奇偶校验位序列，生成编码数据序列 通过复用奇偶校验位序列。

公开(公告)号：US07042964B2

公开(公告)日：2006-05-09

申请号：US10023543

申请日：2001-12-17

申请人： Markus Muck ,  Ralf Hekmann

发明人： Markus Muck ,  Ralf Hekmann

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03M13/6325 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6502 ,  H04L1/0054

摘要： A Viterbi decoder includes a number of classical Add-Compare-Select units and a number of further Add-Compare-Select unit having a lower complexity butterfly unit (300) having only two adder means, such that the further Add-Compare-Select unit has a butterfly unit (300) comprising: first adder means (310) for receiving a first path metric and a branch metric and for producing at its output the addition thereof; and second adder means (320) for receiving a second path metric and said branch metric and for producing at its output the addition thereof. First comparator means (330) are coupled to receive the output of the second adder means and coupled to receive the first path metric for comparing therebetween. Second comparator means (340) are coupled to receive the output of the first adder means and coupled to receive the second path metric for comparing therebetween. First selection means (350) for selecting between the second adder means output and the first path metric produce a first survivor path metric in dependence on the first comparator means comparison. Second selection means (360) for selecting between the first adder means output and the second path metric signal produce a second survivor path metric in dependence on the second comparator means comparison. Only two adder means are used for processing metric transitions as a second branch metric is identified as having a value of zero.

摘要翻译： 维特比解码器包括多个经典的加法比较选择单元和多个具有仅具有两个加法器装置的较低复杂性蝶形单元（300）的另外的加法比较选择单元，使得进一步的加法比选择单元 具有蝶形单元（300），包括：第一加法器装置（310），用于接收第一路径度量和分支度量，并在其输出端产生加法; 以及第二加法器装置（320），用于接收第二路径度量和所述分支度量，并用于在其输出端产生其相加。 第一比较器装置（330）被耦合以接收第二加法器装置的输出并被耦合以接收用于在它们之间比较的第一路径量度。 第二比较器装置（340）被耦合以接收第一加法器装置的输出并被耦合以接收用于在它们之间比较的第二路径量度。 用于在第二加法器装置输出和第一路径度量之间进行选择的第一选择装置（350）根据第一比较器装置比较产生第一幸存路径量度。 用于在第一加法器装置输出和第二路径度量信号之间进行选择的第二选择装置（360）根据第二比较器装置比较产生第二幸存路径量度。 只有两个加法器装置用于处理度量转换，因为第二分支度量被标识为具有零值。

公开(公告)号：US06940928B2

公开(公告)日：2005-09-06

申请号：US09952312

申请日：2001-09-12

申请人： Kelly B. Cameron

发明人： Kelly B. Cameron

IPC分类号： H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  H04L27/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Soft In Soft Out Turbo Code Decoder. Metrics are received by a decoder having SISO unit(s). The SISO unit computes all the alpha values corresponding to a block of data. Of the alpha values computed some alpha values, for example alpha values selected at regular intervals, corresponding to checkpoint values are pushed on a checkpoint stack. Alpha values are computed with some being saved as checkpoint values and some being discarded are computed until the computation reaches a predetermined distance from the end of the block of data. Once the predetermined distance is reached all alpha values are pushed on a computation stack. Once all the values corresponding to the values between the predetermined end of the block and the end of the block have been computed and placed in the computation stack they may be combined with beta values to produce extrinsic values. Once all the values have been used from the computation stack the next checkpoint value can be used to compute another computation stack of alpha values. The alpha values can then be combined with beta values to form extrinsic values and the process continued.

摘要翻译： 软输出Turbo码解码器的方法和装置。 度量由具有SISO单元的解码器接收。 SISO单元计算对应于数据块的所有α值。 计算一些alpha值的Alpha值，例如以定期间隔选择的对应于检查点值的alpha值被推送到检查点堆栈。 计算Alpha值，其中一些被保存为检查点值，并且计算一些被丢弃的值，直到计算达到距数据块结束的预定距离。 一旦达到预定距离，所有的阿尔法值被推送到计算堆栈上。 一旦对应于块的预定端和块结束之间的值的所有值已经被计算并被放置在计算堆栈中，它们可以与β值组合以产生外在值。 一旦从计算堆栈中使用了所有的值，可以使用下一个检查点值来计算alpha值的另一个计算堆栈。 然后可以将α值与β值组合以形成外在值，并且该过程继续。

公开(公告)号：US20030026346A1

公开(公告)日：2003-02-06

申请号：US10048915

申请日：2002-02-05

发明人： Wataru Matsumoto ,  Masafumi Narikawa

IPC分类号： H04L005/12 ,  H04L023/02 ,  H03M013/03

CPC分类号： H04L1/0071 ,  H03M13/1515 ,  H03M13/258 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2966 ,  H03M13/2975 ,  H03M13/3988 ,  H04L1/0066 ,  H04L1/007 ,  H04L1/04

摘要： The communication apparatus comprises a turbo encoder. This turbo encoder includes a first recursive systematic convolutional encoder which convolutionally encodes two information bit sequences to output first redundant data, and a second recursive systematic convolutional encoder which convolutionally encodes the information bit sequences subjected to an interleave process to output second redundant data. The first and second recursive systematic convolutional encoders are encoders which search all connection patterns constituting the encoders and which satisfy optimum conditions that an interval between two bits null1null of a self-terminated pattern is maximum in a specific block length and that a total weight in the pattern having the maximum interval is maximum in the specific block length.

摘要翻译： 通信装置包括turbo编码器。 该turbo编码器包括对两个信息比特序列进行卷积编码以输出第一冗余数据的第一递归系统卷积编码器，以及对经过交织处理的信息比特序列进行卷积编码以输出第二冗余数据的第二递归系统卷积编码器。 第一和第二递归系统卷积编码器是编码器，其搜索构成编码器的所有连接图案，并且满足最终条件，即自终端图案的两个比特“1”之间的间隔在特定块长度中最大，而总重量 在特定块长度中具有最大间隔的图案是最大的。

公开(公告)号：US20020061070A1

公开(公告)日：2002-05-23

申请号：US09952455

申请日：2001-09-12

发明人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L005/12

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US20020061069A1

公开(公告)日：2002-05-23

申请号：US09952309

申请日：2001-09-12

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L005/12

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*) operation to receive the metrics and a priori values as well as forming min star structures from individual min star operations. Two separate outputs from the min star operation may be maintained separately throughout all calculations and combined only when a final value is required. In addition input to the min star operators that are available prior to a particular decoder iteration may be combined separately to allow an increase in speed within decoding iterations. The same principals apply to the more popular max star operation.

摘要翻译： 用于在地图解码器中执行前向（alpha）和反向（beta）度量的计算的方法和装置。 该方法包括使用最小星号（min *）操作来接收度量和先验值，以及从单个最小星号操作形成最小星型结构。 在所有计算过程中，可以分别维护来自min Star操作的两个独立的输出，并且仅在需要最终值时进行组合。 此外，在特定解码器迭代之前可用的最小星号运算符的输入可以单独组合以允许解码迭代中的速度增加。 相同的原则适用于更受欢迎的最大星号操作。

公开(公告)号：US20020048329A1

公开(公告)日：2002-04-25

申请号：US09952210

申请日：2001-09-12

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Thomas A. Hughes

IPC分类号： H04L027/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Min star calculations in a Map decoder. Min star calculations are performed by a circuit that includes a first circuit that performs an Min(A,B) operation simultaneously with a circuit that calculates a nulllog(1nullenullnullAnullBnull) value. The sign bit of the AnullB calculation is used to select whether A or B is a minimum. The AnullB calculation is also used to select either nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) as the correct calculation. In order to hasten the selection of either nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) as the correct calculation the apparatus does not wait for the AnullB calculation to complete. Any bit of the AnullB calculation between the third bit and final (sign bit) can be used for the selection. If an incorrect value is selected a log saturation circuit may correct the value. In addition an offset may be added nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) to assure that the calculation does not become negative, necessitating the use of an additional sign bit thereby increasing circuit complexity and slowing down the calculation. Additionally the log terms are computed based on a partial result of the AnullB calculation.

摘要翻译： 地图解码器中Min Star计算的方法和装置。 最小星号计算由包括与计算-log（1 + e- | A-B |）值的电路同时执行Min（A，B）操作的第一电路的电路执行。 A-B计算的符号位用于选择A或B是否为最小值。 A-B计算也用于选择-log（1 + e- | A-B |）或-log（1 + e- | B-A |）作为正确的计算。 为了加快-log（1 + e- | A-B |）或-log（1 + e- | B-A |）的选择作为正确的计算，装置不等待A-B计算完成。 第三位和第三位（符号位）之间的A-B计算的任何位都可用于选择。 如果选择了不正确的值，日志饱和电路可能会更正该值。 此外，可以添加一个偏移量-log（1 + e- | AB |）或-log（1 + e- | BA |），以确保计算不变为负值，从而需要使用附加符号位，从而增加 电路复杂度和计算速度减慢。 另外，基于A-B计算的部分结果来计算对数项。

公开(公告)号：US20010000706A1

公开(公告)日：2001-05-03

申请号：US09741969

申请日：2000-12-20

发明人： Brian K. Butler ,  Gwain Bayley ,  David Hansquine ,  Edward G. Tiedemann JR.

IPC分类号： H04L005/12 ,  H04L023/02

CPC分类号： H04L1/0071 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6325 ,  H03M13/6508 ,  H03M13/6583 ,  H04L1/0054

摘要： The certainties of transmitted bits at predetermined locations in time are determined a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

摘要翻译： 先前确定预定位置处的发送位的确定性。 然后，该信息用于根据发送的比特的确定性将维特比解码器的状态设置为不同的状态度量。 发送位的高确定性导致将与该位相对应的状态重置为高状态度量。 相比之下，传输位的低确定性导致将与该位相对应的状态重置为低状态度量。 将状态重置为不同的状态度量可以提高解码性能，并通过消除不可能的路径缩短融合解码网格所需的时间。