公开(公告)号：US20230045990A1

公开(公告)日：2023-02-16

申请号：US17574059

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Chun Sum Yeung ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.

公开(公告)号：US20230027877A1

公开(公告)日：2023-01-26

申请号：US17959724

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Kulachet Tanpairoj ,  Stephen Hanna

IPC: G06F9/48 ,  G06F12/0875

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

公开(公告)号：US11454941B2

公开(公告)日：2022-09-27

申请号：US16510662

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David A. Palmer

IPC: G05B19/042 ,  H01L21/66 ,  G11C5/14

Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each die of a plurality of dice in the power network, a first signal indicating that the respective die of the plurality of dice is in a high current state or a second signal indicating that the respective die of the plurality of dice is an active current state. The received signals include at least one second signal. The first die determines, based upon the received signals, a number of dice of the plurality of dice that are currently active and selects an activity threshold based upon that number. The first die further determines an activity level for the power network and transmits, to the plurality of dice, the first signal indicating that the first die is in the high current state in response to determining that the activity level is less than the activity threshold.

公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20220164301A1

公开(公告)日：2022-05-26

申请号：US17105053

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F13/16 ,  G06F1/12

Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

公开(公告)号：US20220100674A1

公开(公告)日：2022-03-31

申请号：US17495410

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan S. Parry

IPC: G06F12/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

公开(公告)号：US11194643B1

公开(公告)日：2021-12-07

申请号：US16891615

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/07 ,  G06F11/30

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US11062740B2

公开(公告)日：2021-07-13

申请号：US16834293

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C5/14 ,  G11C7/22

Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.

公开(公告)号：US10692562B2

公开(公告)日：2020-06-23

申请号：US16734241

申请日：2020-01-03

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/16 ,  G11C11/00 ,  G11C11/22 ,  G11C13/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US20190371392A1

公开(公告)日：2019-12-05

申请号：US16543477

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.