公开(公告)号：US11201111B2

公开(公告)日：2021-12-14

申请号：US16697560

申请日：2019-11-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Zhiping Zhang ,  Peng Zhang ,  Deepanshu Dutta

IPC: H01L27/11578 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

公开(公告)号：US11081180B2

公开(公告)日：2021-08-03

申请号：US16842112

申请日：2020-04-07

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C11/56 ,  G06F11/10 ,  G11C16/10 ,  G11C16/08 ,  G06F11/18 ,  H01L27/11556 ,  G11C16/34 ,  G11C16/24

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

公开(公告)号：US11062780B1

公开(公告)日：2021-07-13

申请号：US16729951

申请日：2019-12-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Jiahui Yuan ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.

公开(公告)号：US11024393B1

公开(公告)日：2021-06-01

申请号：US16738677

申请日：2020-01-09

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.

公开(公告)号：US20210134372A1

公开(公告)日：2021-05-06

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

公开(公告)号：US20210134370A1

公开(公告)日：2021-05-06

申请号：US16701450

申请日：2019-12-03

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10984867B1

公开(公告)日：2021-04-20

申请号：US16724876

申请日：2019-12-23

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Sarath Chandran Puthen Thermadam ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

Abstract: A memory apparatus and method of operation are provided. The apparatus includes first memory cells coupled to control circuit and a particular word line and storing a first cell data. The apparatus also includes second memory cells coupled to a source side neighbor word line disposed on a source side of the particular word line and storing second cell threshold voltages programmed after the first cell data. The control circuit senses the second cell threshold voltages at a first time while applying a predetermined initial read voltage to the source side neighbor word line. The control circuit senses the first cell data at a second time while iteratively applying one of a plurality of particular read voltages to the particular word line and simultaneously and iteratively applying one of a plurality of neighbor pass voltages to the source side neighbor word line based on the second cell threshold voltages.

公开(公告)号：US10910075B2

公开(公告)日：2021-02-02

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US10811089B2

公开(公告)日：2020-10-20

申请号：US16829888

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

公开(公告)号：US10770165B1

公开(公告)日：2020-09-08

申请号：US16571844

申请日：2019-09-16

Applicant: SanDisk Technologies LLC

Inventor： Xue Qing Cai ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C29/50 ,  G11C11/4094 ,  G11C11/408

Abstract: Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of a block using a program pulse with an initial magnitude, Vpgm. By reading the memory cells, Vpgm can be optimized for programming subsequent word lines. The subsequent word lines may be programmed using a no-verify program operation followed by a word line short circuit test, for one or more word lines involved in the program operation. The short circuit test can be performed concurrently on a single word line, multiple word lines and/or one or more sub-blocks of a block, based on an amount of write data which can be storage by a controller.