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公开(公告)号：US11423993B2
公开(公告)日：2022-08-23
申请号：US16676023
申请日：2019-11-06
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Peng Zhang , Dengtao Zhao , Deepanshu Dutta
Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
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2.发明授权公开(公告)号：US11081184B2
公开(公告)日：2021-08-03
申请号：US16701450
申请日：2019-12-03
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
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公开(公告)号：US20210257037A1
公开(公告)日：2021-08-19
申请号：US16793749
申请日：2020-02-18
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.
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公开(公告)号：US11244735B2
公开(公告)日：2022-02-08
申请号：US16793749
申请日：2020-02-18
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.
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公开(公告)号：US20210202011A1
公开(公告)日：2021-07-01
申请号：US16729951
申请日：2019-12-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Jiahui Yuan , Dengtao Zhao , Deepanshu Dutta
Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.
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Patent Agency Ranking
公开(公告)号：US20210134369A1
公开(公告)日：2021-05-06
申请号：US16668675
申请日：2019-10-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
IPC: G11C16/10 , G11C16/24 , G11C11/4074 , G11C11/409
Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
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公开(公告)号：US11201111B2
公开(公告)日：2021-12-14
申请号：US16697560
申请日：2019-11-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Dengtao Zhao , Zhiping Zhang , Peng Zhang , Deepanshu Dutta
IPC: H01L27/11578 , H01L23/522 , H01L23/528 , G11C5/06 , G11C16/16 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11519
Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.
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公开(公告)号：US11062780B1
公开(公告)日：2021-07-13
申请号：US16729951
申请日：2019-12-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Jiahui Yuan , Dengtao Zhao , Deepanshu Dutta
Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.
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公开(公告)号：US11024393B1
公开(公告)日：2021-06-01
申请号：US16738677
申请日：2020-01-09
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Ken Oowada , Deepanshu Dutta
Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.
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公开(公告)号：US20210134372A1
公开(公告)日：2021-05-06
申请号：US16676023
申请日：2019-11-06
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Peng Zhang , Dengtao Zhao , Deepanshu Dutta
Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
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