公开(公告)号：US20230326530A1

公开(公告)日：2023-10-12

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5621

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US20230238062A1

公开(公告)日：2023-07-27

申请号：US17583570

申请日：2022-01-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.

公开(公告)号：US20230162809A1

公开(公告)日：2023-05-25

申请号：US17533292

申请日：2021-11-23

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang ,  Dengtao Zhao

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

公开(公告)号：US20230101019A1

公开(公告)日：2023-03-30

申请号：US17484218

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

公开(公告)号：US20230097040A1

公开(公告)日：2023-03-30

申请号：US17487347

申请日：2021-09-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/08 ,  G11C16/16

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is coupled to the word lines and bit lines and is configured to apply an unselected top voltage to unselected ones of the top drain-side select gate transistors during a memory operation. The control means is also configured to simultaneously apply a selected top voltage to selected ones top drain-side select gate transistors during the memory operation. The unselected top voltage is intentionally different electrically than the selected top voltage.

公开(公告)号：US20230095757A1

公开(公告)日：2023-03-30

申请号：US17487634

申请日：2021-09-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

公开(公告)号：US20230052121A1

公开(公告)日：2023-02-16

申请号：US17402989

申请日：2021-08-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higanshitani

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G06F16/2458 ,  H04L9/12

Abstract: A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify operations. The programming operations include applying a programming voltage to the selected word line, and the verify operations include applying a verify voltage to the selected word line. At least one programming loop of the plurality of programming loops further includes a pre-verify operation. The pre-verify operation includes applying a pre-read voltage to the selected word line. The pre-read voltage is less than the verify voltage.

公开(公告)号：US11562800B2

公开(公告)日：2023-01-24

申请号：US17343486

申请日：2021-06-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04

Abstract: This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.

公开(公告)号：US11551761B1

公开(公告)日：2023-01-10

申请号：US17461418

申请日：2021-08-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Deepanshu Dutta

IPC: G11C11/04 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C11/56 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/11565

Abstract: In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.

公开(公告)号：US11423996B1

公开(公告)日：2022-08-23

申请号：US17323293

申请日：2021-05-18

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yi Song ,  Fanqi Wu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and arranged in strings. Each of the memory cells is also configured to retain a threshold voltage corresponding to one of a plurality of data states and be erased in an erase operation. A control circuit is coupled to the word lines and the strings and is configured to identify ones of the strings having a faster relative erase speed compared to others of the strings. During the erase operation, the control circuit raises the threshold voltage of the memory cells associated with the ones of the strings having the faster relative erase speed while not raising the threshold voltage of the memory cells associated with the others of the strings.