公开(公告)号：US11803379B2

公开(公告)日：2023-10-31

申请号：US17963317

申请日：2022-10-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Brett L. Huber ,  Duc Bui

IPC: G06F9/30 ,  G06F18/24

CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F18/24

Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

公开(公告)号：US20230325188A1

公开(公告)日：2023-10-12

申请号：US18332817

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/383 ,  G06F9/30047 ,  G06F9/345 ,  G06F9/30112 ,  G06F9/30149

Abstract: A streaming engine employed in a digital signal processor specified a fixed data stream. Once started the data stream is read only and cannot be written. Once fetched, the data stream is stored in a first-in-first-out buffer for presentation to functional units in the fixed order. Data use by the functional unit is controlled using the input operand fields of the corresponding instruction. A read only operand coding supplies the data an input of the functional unit. A read/advance operand coding supplies the data and also advances the stream to the next sequential data elements. The read only operand coding permits reuse of data without requiring a register of the register file for temporary storage.

公开(公告)号：US20230053842A1

公开(公告)日：2023-02-23

申请号：US17972675

申请日：2022-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0815 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

公开(公告)号：US20220197637A1

公开(公告)日：2022-06-23

申请号：US17687780

申请日：2022-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

公开(公告)号：US11334354B2

公开(公告)日：2022-05-17

申请号：US16361449

申请日：2019-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

公开(公告)号：US11269638B2

公开(公告)日：2022-03-08

申请号：US15635449

申请日：2017-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

公开(公告)号：US11226818B2

公开(公告)日：2022-01-18

申请号：US16782580

申请日：2020-02-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

公开(公告)号：US20210397451A1

公开(公告)日：2021-12-23

申请号：US17467550

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/0811 ,  G06F9/345 ,  G06F11/00 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US11182200B2

公开(公告)日：2021-11-23

申请号：US15636686

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F15/76

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

公开(公告)号：US11106591B2

公开(公告)日：2021-08-31

申请号：US16666740

申请日：2019-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F11/10 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0846

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.