公开(公告)号：US06535148B1

公开(公告)日：2003-03-18

申请号：US09249500

申请日：1999-02-12

Applicant: Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  Sugata Ghosal

Inventor： Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  Sugata Ghosal

IPC: H03M700

CPC classification number: H04N19/184 ,  H03M7/30 ,  H04N19/895 ,  H04N19/98

Abstract: A method and apparatus for hardware efficient decoding of compression coefficients. In one embodiment, a numerator of an equation used to compute a compression coefficient is computed. The denominator is also computed. The numerator and denominator values are truncated such that each numerator and denominator are equal in length to a predetermined constant K. A K-bit integer division is then executed to determine the value of the compression constant.

Abstract translation: 一种用于对压缩系数进行硬件有效解码的方法和装置。 在一个实施例中，计算用于计算压缩系数的等式的分子。 也计算分母。 分母和分母值被截断，使得每个分子和分母的长度等于预定的常数K.然后执行K位整数除法以确定压缩常数的值。

公开(公告)号：US06516088B1

公开(公告)日：2003-02-04

申请号：US09429574

申请日：1999-10-28

Applicant: Tetsujiro Kondo ,  Takaya Hoshino ,  Hideo Nakaya ,  Satoshi Inoue ,  Shizuo Chikaoka

Inventor： Tetsujiro Kondo ,  Takaya Hoshino ,  Hideo Nakaya ,  Satoshi Inoue ,  Shizuo Chikaoka

IPC: G06K900

CPC classification number: H04N9/641 ,  H04N7/0145

Abstract: An NTSC signal is supplied to a first area extracting circuit and a second area extracting circuit. The first area extracting circuit extracts class taps from the NTSC signal. The second area extracting circuit extracts predictive taps from the NTSC signal. The first area extracting circuit extracts pixels in predetermined positions from same phase pixels as a considered pixel. Based on level differences between extracted pixels, a pattern detecting section performs a class categorization. A class code determining section generates class codes based on the result of the class categorization and supplies the generated class codes to a coefficient memory. The coefficient memory outputs pre-stored predictive coefficients based on the class codes to a predictive calculating section. The predictive calculating section performs a sum of product calculation of pixel data as predictive taps received from the first area extracting circuit and the predictive coefficients received from the second area extracting circuit and generates for example a component signal Y with the result of the sum of product calculation.

Abstract translation: NTSC信号被提供给第一区域提取电路和第二区域提取电路。 第一区域提取电路从NTSC信号中提取类别抽头。 第二区域提取电路从NTSC信号中提取预测抽头。 第一区域提取电路从与所考虑的像素相同的相位像素提取预定位置的像素。 基于提取的像素之间的级别差异，图案检测部分执行类别分类。 类代码确定部分基于类分类的结果生成类代码，并将生成的类代码提供给系数存储器。 系数存储器将基于类代码的预先存储的预测系数输出到预测计算部。 预测计算部分执行像素数据的乘积计算的和作为从第一区域提取电路接收的预测抽头和从第二区域提取电路接收的预测系数，并且产生例如产品和之和的分量信号Y 计算。

公开(公告)号：US06480630B1

公开(公告)日：2002-11-12

申请号：US09254536

申请日：1999-03-09

Applicant: Tetsujiro Kondo

Inventor： Tetsujiro Kondo

IPC: G06K936

CPC classification number: H04N19/59 ,  H04N7/0145 ,  H04N19/124 ,  H04N19/132 ,  H04N19/30 ,  H04N19/48 ,  H04N19/50 ,  H04N19/587 ,  H04N19/593 ,  H04N19/70 ,  H04N19/89 ,  H04N19/98

Abstract: An integrative encoding system for encoding and transmitting a plurality of video signals having different resolutions that correspond to a plurality of display units. The integrative encoding system has a compression processor, an editing processor, and an integrated services digital broadcasting (ISDB) transmitter. The compression processor performs adaptive dynamic range coding (ADRC) to compress each of said plurality of video signals on a block basis by reducing the dynamic range. An adaptive decoding system receives and decodes the transmitted plurality of video signals for display by the plurality of display units.

Abstract translation: 一种用于对与多个显示单元相对应的具有不同分辨率的多个视频信号进行编码和发送的综合编码系统。 综合编码系统具有压缩处理器，编辑处理器和综合业务数字广播（ISDB）发射机。 压缩处理器通过减小动态范围来执行自适应动态范围编码（ADRC）以块为基础压缩所述多个视频信号中的每一个。 自适应解码系统接收并解码所发送的多个视频信号以供多个显示单元显示。

公开(公告)号：US06473876B1

公开(公告)日：2002-10-29

申请号：US09342287

申请日：1999-06-29

Applicant: Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  William Knox Carey

Inventor： Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  William Knox Carey

IPC: G06F1100

CPC classification number: H04N19/88 ,  H04N19/89 ,  H04N19/895 ,  H04N19/98

Abstract: The present invention includes a system and method for encoding data by altering data of a rotation block by a rotation factor dependent on data of a key block. In one embodiment, the data includes compression parameters that are descriptive of compressed data. In one embodiment, data of the second or rotation block is altered by calculating a rotation factor from data of a first or key block and altering data of second block in accordance with the rotation factor. In another embodiment, the present invention includes a method for recovering data when there are data losses by determining candidate rotation values for full decoding data of the second block and selecting a rotation value from the candidate rotation values corresponding to the first block data.

Abstract translation: 本发明包括一种通过根据关键块的数据的旋转因子改变旋转块的数据来对数据进行编码的系统和方法。 在一个实施例中，数据包括描述压缩数据的压缩参数。 在一个实施例中，通过根据旋转因子从第一或关键块的数据计算旋转因子和改变第二块的数据来改变第二或旋转块的数据。 在另一个实施例中，本发明包括一种当通过确定用于第二块的完全解码数据的候选旋转值并且从与第一块数据相对应的候选旋转值中选择旋转值而存在数据丢失时恢复数据的方法。

公开(公告)号：US06442297B1

公开(公告)日：2002-08-27

申请号：US09241683

申请日：1999-02-01

Applicant: Tetsujiro Kondo ,  Akihiro Okumura

Inventor： Tetsujiro Kondo ,  Akihiro Okumura

IPC: G06K946

CPC classification number: G06T9/007

Abstract: Apparatus and method for performing hierarchical coding without utilizing a delay circuit arranged separately from a memory for storing images. In the case where one second-layer pixel is formed from 2×2 first-layer pixels, three of the 2×2 first-layer pixels used to form the one second-layer pixel (excluding one final input pixel) are read out from a first-layer memory when the final input pixel is input. The three pixels read out are supplied to an adder which computes the sum thereof and supplies the sum value to an adder-subtracter. The adder-subtracter computes the sum of the sum value from the adder and the final input pixel so as to obtain the one second-layer pixel. Such second-layer pixel is supplied to a second-layer memory to be stored therein. The final input pixel is not stored in the first-layer memory.

Abstract translation: 用于执行分层编码而不利用与用于存储图像的存储器分开布置的延迟电路的装置和方法。 在从2×2个第一层像素形成一个第二层像素的情况下，用于形成一个第二层像素（不包括一个最终输入像素）的2×2个第一层像素中的三个从第一层 输入最终输入像素时的存储器。 读出的三个像素被提供给加法器，该加法器计算其和，并将和值提供给加法器 - 减法器。 加法器 - 减法器计算来自加法器和最终输入像素的和值的和，以获得一个第二层像素。 这样的第二层像素被提供给存储在其中的第二层存储器。 最终输入像素不存储在第一层存储器中。

公开(公告)号：US06389562B1

公开(公告)日：2002-05-14

申请号：US09342322

申请日：1999-06-29

Applicant: Tetsujiro Kondo ,  Yasuhiro Fujimori ,  William Knox Carey ,  James J. Carrig

Inventor： Tetsujiro Kondo ,  Yasuhiro Fujimori ,  William Knox Carey ,  James J. Carrig

IPC: G06F1100

CPC classification number: H04N19/88 ,  H04N19/895

Abstract: Data is encoded to maximize subsequent recovery of lost or damaged compression parameters of encoded data. In one embodiment, at least one compression parameter is used to define a pseudorandom sequence and the data is shuffled using the pseudorandom sequence. In one embodiment, a bit reallocation process and code reallocation process are performed on the data to randomize the data.

Abstract translation: 编码数据以最大化后续恢复编码数据的丢失或损坏的压缩参数。 在一个实施例中，使用至少一个压缩参数来定义伪随机序列，并且使用伪随机序列对数据进行混洗。 在一个实施例中，对数据执行位重新分配处理和代码重新分配处理以使数据随机化。

公开(公告)号：US06370546B1

公开(公告)日：2002-04-09

申请号：US08829407

申请日：1997-03-31

Applicant: Tetsujiro Kondo

Inventor： Tetsujiro Kondo

IPC: G06F1730

CPC classification number: G06F13/28 ,  Y10S707/99938 ,  Y10S707/99952

Abstract: An information processing system comprises a first information processing device and a second information processing device connected to the first information processing device. Here, the first information processing device comprises a first connection device connected to the first information processing device, a first memory for storing information and a first processor for processing information. The second information processing device comprises a second connection device connected to the first connection device, a second memory for storing information and a second processor for processing information. The first processor directly accesses the second memory of the second information processing device to read and write information and the second processor directly accesses the first memory of the first information processing device to read and write information. The above is configured so as to be capable of managing information files in common and improving operativity while simplifying management of information files and maintaining secrecy.

Abstract translation: 信息处理系统包括连接到第一信息处理设备的第一信息处理设备和第二信息处理设备。 这里，第一信息处理装置包括连接到第一信息处理装置的第一连接装置，用于存储信息的第一存储器和用于处理信息的第一处理器。 第二信息处理装置包括连接到第一连接装置的第二连接装置，用于存储信息的第二存储器和用于处理信息的第二处理器。 第一处理器直接访问第二信息处理设备的第二存储器以读取和写入信息，并且第二处理器直接访问第一信息处理设备的第一存储器以读取和写入信息。 上述配置为能够共同地管理信息文件并提高可操作性，同时简化信息文件的管理并保持秘密。

公开(公告)号：US06356310B1

公开(公告)日：2002-03-12

申请号：US09632057

申请日：2000-08-03

Applicant: Takashi Horishi ,  Tetsujiro Kondo ,  Hideo Nakaya

Inventor： Takashi Horishi ,  Tetsujiro Kondo ,  Hideo Nakaya

IPC: H01N701

CPC classification number: H04N7/0137 ,  H04N5/145 ,  H04N7/0122 ,  H04N7/0125 ,  H04N9/64

Abstract: A delay register section 31 holds SD pixels of a luminance signal and a classification section 33 decides a class, reads a coefficient corresponding to the decision result from a coefficient RAM section 40, and outputs the coefficient to a product-sum section 38. The product-sum section 38 captures the pixel data for 17 taps from the delay register section 31, converts the pixel data into seven taps, and outputs them to the product-sum section 38. The product-sum section 38 performs the product-sum operation of pixel data and coefficients and outputs the operation result as HD pixels. An interpolation pixel operation section 42 applies a simple interpolation processing different from the case of a luminance signal to the pixel data of a color signal component to generate HD pixels of a color signal. Thus, downsizing and cost reducing can be realized.

Abstract translation: 延迟寄存器部31保持亮度信号的SD像素，分类部33决定分类，从系数RAM部40读取与判定结果对应的系数，并将该系数输出到积存部38。 - 片段38从延迟寄存器部分31捕获17个抽头的像素数据，将像素数据转换成七个抽头，并将它们输出到产品总和部分38.产品总和部分38执行产品和操作 像素数据和系数，并将该运算结果作为HD像素输出。 内插像素运算部42将与亮度信号不同的简单插值处理应用于彩色信号分量的像素数据，生成彩色信号的HD像素。 因此，可以实现小型化和降低成本。

公开(公告)号：US06335988B1

公开(公告)日：2002-01-01

申请号：US08904930

申请日：1997-08-01

Applicant: Tetsujiro Kondo

Inventor： Tetsujiro Kondo

IPC: G06K936

CPC classification number: H04N5/781 ,  H04N5/772 ,  H04N5/85 ,  H04N5/9261 ,  H04N7/54 ,  H04N9/8042 ,  H04N9/8045 ,  H04N19/20 ,  H04N19/23 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/61 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4316 ,  H04N21/4347 ,  H04N21/44008 ,  H04N21/4435 ,  H04N21/8153

Abstract: A transmitter which allows to reproduce a high quality and smooth dynamic image on the receiving side even with a transmission medium having a low transmission rate is provided. Background plane data representing a still image of a background image of video and one or more motion plane data representing still images of each of moving objects moving on the background image are separated from input digital video signal. The separated background plane data and each motion plane data are stored individually in memories 23BG and 23A1 through 23An. Change data on the still images stored as the motion plane data is detected based on the input digital video signal and output of the memories 23BG and 23A1 through 23An to compress and code it by a coding means 26. Still image data of the plurality of plane data of the memory means 23BG and 23A1 through 23An and the change information from the coding means 26 are transmitted.

Abstract translation: 提供了一种允许在接收侧再现高质量和平滑的动态图像的发射机，即使是具有低传输速率的传输介质。 表示视频的背景图像的静止图像的背景平面数据和表示在背景图像上移动的每个移动物体的静止图像的一个或多个运动平面数据与输入数字视频信号分离。 分离的背景平面数据和每个运动平面数据分别存储在存储器23BG和23A1至23An中。 基于输入的数字视频信号和存储器23BG和23A1至23An的输出来检测作为运动平面数据存储的静止图像上的数据，以由编码装置26进行压缩和编码。多个平面的静止图像数据 发送存储装置23BG和23A1至23An的数据和来自编码装置26的改变信息。

公开(公告)号：US06311297B1

公开(公告)日：2001-10-30

申请号：US09111362

申请日：1998-07-06

Applicant: Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  Sugata Ghosal

Inventor： Tetsujiro Kondo ,  James J. Carrig ,  Yasuhiro Fujimori ,  Sugata Ghosal

IPC: H04N521

CPC classification number: H04N19/85 ,  H04N5/21 ,  H04N5/4401 ,  H04N19/59 ,  H04N19/88 ,  H04N19/89 ,  H04N19/895 ,  H04N19/98

Abstract: A method and apparatus for generating blocks of data for an image is described. An image is divided into a localized area. For each localized area, pixels are assigned to blocks following a complementary pattern. The complementary pattern is designed such that most pixels are adjacent to pixels arising from other blocks. The neighboring pixels provide information that is useful for reconstructing data that is lost due to burst error. In one embodiment, this is used in the transmission of video signals over a potentially lossy communications channel.

Abstract translation: 描述用于生成图像的数据块的方法和装置。 图像被分为局部区域。 对于每个局部区域，像素被分配到跟随互补模式的块。 互补图案被设计成使得大多数像素与其他块产生的像素相邻。 相邻像素提供对重建由于突发错误而丢失的数据有用的信息。 在一个实施例中，这用于通过潜在有损耗的通信信道传输视频信号。