公开(公告)号：US10522415B1

公开(公告)日：2019-12-31

申请号：US16562454

申请日：2019-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/82

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.

公开(公告)号：US10453849B2

公开(公告)日：2019-10-22

申请号：US15936396

申请日：2018-03-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

IPC: H01L29/02 ,  H01L27/108 ,  G11C11/401

Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

公开(公告)号：US10446473B1

公开(公告)日：2019-10-15

申请号：US16250485

申请日：2019-01-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Ding-Lung Chen ,  En-Feng Liu ,  Yu-Cheng Tung

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/40 ,  H01L23/48 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.

公开(公告)号：US10431457B2

公开(公告)日：2019-10-01

申请号：US15361085

申请日：2016-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/70 ,  H01L21/027 ,  G03F7/00 ,  G03F7/20

Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.

公开(公告)号：US10381439B2

公开(公告)日：2019-08-13

申请号：US16053794

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/06 ,  H01L21/306 ,  H01L23/535 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775

Abstract: A nanowire transistor includes: a nanowire channel layer on a substrate; a gate structure on and around the nanowire channel layer, wherein the gate structure comprises a high-k dielectric layer on the nanowire channel layer; a first spacer on a lateral sidewall of the gate structure, wherein a lateral sidewall of the first spacer is aligned with a lateral sidewall of the nanowire channel layer; a second spacer on the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer, wherein top surfaces of the first spacer and the second spacer are coplanar and the second spacer contacts the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer directly; and a source/drain structure adjacent to two sides of the second spacer.

公开(公告)号：US10355019B1

公开(公告)日：2019-07-16

申请号：US16024906

申请日：2018-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Ding-Lung Chen ,  Yu-Cheng Tung

IPC: H01L27/12 ,  H01L27/06 ,  H01L27/092 ,  H01L29/786 ,  H01L23/528 ,  H01L29/861

Abstract: A semiconductor device includes a substrate, a first transistor, a first diode structure, and a second diode structure. The first transistor is disposed on the substrate. The first transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the substrate by the first diode structure. The first drain electrode is connected to the substrate by the second diode structure. The first diode structure and the second diode structure may be used to improve potential unbalance in the transistor, and operation performance and reliability of the semiconductor device may be enhanced accordingly.

公开(公告)号：US10283413B2

公开(公告)日：2019-05-07

申请号：US15264590

申请日：2016-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/82

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US20190131456A1

公开(公告)日：2019-05-02

申请号：US15828060

申请日：2017-11-30

Applicant: United Microelectronics Corp.

Inventor： Shao-Hui Wu ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258 ,  H01L27/092

Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

公开(公告)号：US10276476B1

公开(公告)日：2019-04-30

申请号：US15981955

申请日：2018-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Ding-Lung Chen ,  En-Feng Liu ,  Yu-Cheng Tung

IPC: H01L23/48 ,  H01L23/52 ,  H01L27/12 ,  H01L29/786 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L23/532

Abstract: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.

公开(公告)号：US10256240B2

公开(公告)日：2019-04-09

申请号：US15925780

申请日：2018-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/267

Abstract: A semiconductor device includes a substrate having a first region and a second region, a fin-shaped structure and a bump on the first region of the substrate, and a shallow trench isolation (STI) around the fin-shaped structure and on the bump. Preferably, the fin-shaped structure and the bump comprise different material, the fin-shaped structure comprises a top portion and a bottom portion, the top portion and the bottom portion comprise different semiconductor material, and a top surface of the bottom portion is lower than a top surface of all of the STI on both the first region and the second region and higher than a top surface of the bump and the top surface of the bump contacts the STI directly.