公开(公告)号：US6018256A

公开(公告)日：2000-01-25

申请号：US809895

申请日：1997-03-07

申请人： Takashi Kumagai ,  Yasunobu Tokuda

发明人： Takashi Kumagai ,  Yasunobu Tokuda

IPC分类号： G11C7/10 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0948 ,  H03K3/00 ,  H03B1/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/0948

摘要： An output circuit which outputs a data signal from an output terminal after setting the output terminal to a potential intermediate between a power supply line potential and a ground line potential. The output circuit includes an output drive configured of first and second transistors. The first transistor has a first control terminal to which is input a first control signal. The second transistor has a second control terminal to which is input a second control signal. It further includes a setting member which controls the first and second control signals to set the first and second transistors to the off state. It further includes a shorting member which shorts one of the first and second control terminals and the output terminal. Moreover, before the data signal is output, the transistors are set to the off state by the setting member, after which shorting is carried out according to the potential of the output terminal, and the output terminal is set to an intermediate potential.

摘要翻译： PCT No.PCT / JP96 / 01851 Sec。 371日期1997年3月7日 102（e）1997年3月7日PCT PCT 1996年7月4日PCT公布。 公开号WO97 / 03498 日期1997年1月30日在将输出端子设定为电源线电位与接地线电位之间的电位的输出电路时，输出来自输出端子的数据信号。 输出电路包括由第一和第二晶体管构成的输出驱动器。 第一晶体管具有输入第一控制信号的第一控制端。 第二晶体管具有输入第二控制信号的第二控制端。 它还包括设置部件，其控制第一和第二控制信号以将第一和第二晶体管设置为断开状态。 还包括使第一和第二控制端子和输出端子之一短路的短路构件。 此外，在输出数据信号之前，晶体管被设定部件设定为截止状态，之后根据输出端子的电位进行短路，将输出端子设定为中间电位。

公开(公告)号：US5914618A

公开(公告)日：1999-06-22

申请号：US814875

申请日：1997-03-11

申请人： Derwin W. Mattos

发明人： Derwin W. Mattos

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0185 ,  H04L13/08

CPC分类号： H03K19/00361 ,  H03K17/167

摘要： An I/O buffer with minimized footprint; which is less susceptible to voltage spikes caused by switching noise, and which is adapted for used in a separate power bus arrangement. The buffer minimizes voltage spikes caused by switching noise by replacing the single large current surge that occurs during switching with smaller current surges at different times. This is accomplish by having two different drivers for the transitional and holding phases: a Transient Switching Circuit (TSC) and a Logic Holding Circuit (LHC). Generally, the TSC is operational to cause a change in the output signal when there is a change in the input signal. Conversely, the LHC is operational subsequent to the logic transition occurrence at the input signal to bring the output signal to the rail voltage.

摘要翻译： I / O缓冲器，占用空间最小; 其不易受到由开关噪声引起的电压尖峰的影响，并且适用于单独的电源总线布置。 缓冲器通过在不同时间更换较小的电流浪涌来替换开关期间发生的单个大电流浪涌，从而最大限度地减少由开关噪声引起的电压尖峰。 这通过为过渡和保持阶段提供两个不同的驱动器来实现：瞬态开关电路（TSC）和逻辑保持电路（LHC）。 通常，当输入信号有变化时，TSC可操作地引起输出信号的变化。 相反，在输入信号上的逻辑转换发生之后，LHC正在运行，以使输出信号达到轨电压。

公开(公告)号：US5644252A

公开(公告)日：1997-07-01

申请号：US613409

申请日：1996-03-11

申请人： Seiichi Watarai

发明人： Seiichi Watarai

IPC分类号： H03K19/0175 ,  G06F13/40 ,  H03K17/16 ,  H03K19/0952 ,  H04L25/02 ,  H04L25/03

CPC分类号： H04L25/0278 ,  G06F13/4072 ,  H03K17/167 ,  H04L25/028 ,  H04L25/03834

摘要： In order to effectively interface a plurality of integrated circuits to a bus, an improved driver is disclosed. The driver includes an inverter provided between a power source and a ground level, and an output transistor whose gate is coupled to an output of the inverter and whose source-drain path is coupled between an output of the driver and the second power source. A feedback path is coupled between the output of the driver and the output of the inverter. The feedback path includes first and second transistors coupled in series. The first transistor has its gate coupled to an input of the inverter, while the second transistor has its gate coupled to the output of the inverter via delay means. The driver is characterized by an impedance controller which is provided between the output of the inverter and the second power source. The impedance controller stepwisely adjusts impedance of the output transistor when an input signal to the inverter changes from a low logic level to a high logic level. As an alternative to or in combination of the impedance controller, another impedance controller is provided which is provided in parallel with the second transistor and which stepwisely adjusts the impedance of the output transistor when the input signal to the inverter changes from the low logic level to the high logic level.

摘要翻译： 为了有效地将多个集成电路接口到总线，公开了一种改进的驱动器。 驱动器包括设置在电源和地电平之间的反相器，以及输出晶体管，其栅极耦合到反相器的输出并且其源极 - 漏极路径耦合在驱动器的输出端和第二电源之间。 反馈路径耦合在驱动器的输出和反相器的输出之间。 反馈路径包括串联耦合的第一和第二晶体管。 第一晶体管的栅极耦合到反相器的输入端，而第二晶体管的栅极通过延迟装置耦合到反相器的输出端。 驱动器的特征在于阻抗控制器，其设置在逆变器的输出端和第二电源之间。 当逆变器的输入信号从低逻辑电平变为高逻辑电平时，阻抗控制器逐步调整输出晶体管的阻抗。 作为阻抗控制器的替代或组合，提供了另一个阻抗控制器，其与第二晶体管并联提供，并且当逆变器的输入信号从低逻辑电平变化到阶跃地调节输出晶体管的阻抗时 高逻辑水平。

公开(公告)号：US5293082A

公开(公告)日：1994-03-08

申请号：US71598

申请日：1993-06-04

申请人： Mehdi Bathaee

发明人： Mehdi Bathaee

IPC分类号： H03K17/16 ,  H03K4/26 ,  H03K5/01

CPC分类号： H03K17/167

摘要： A capacitive load is charged and/or discharged in sequential current steps, thereby rapidly changing the charge on the capacitive load. The stepwise change in load current can be effected by a plurality of parallel output driver stages each of which is much smaller, and thus generates less noise, than a single output driver stage with the same overall current carrying capacity. The output driver stages are connected to the load so as to be sequentially actuated responsive to an input signal representative of the binary state to be coupled by the output drive to the load. The input signal is connected to the respective output driver stages by predriver stages. Except for the lowest order predriver stage, each predriver stage has an enable circuit that switches on the driver stage at the desired point in the transition interval between binary states.

摘要翻译： 电容负载以连续的电流步进充电和/或放电，从而快速改变电容性负载上的电荷。 负载电流的逐步变化可以通过多个并联输出驱动级来实现，每个并联输出驱动级比具有相同总载流容量的单个输出驱动器级小得多，因此产生较少的噪声。 输出驱动器级连接到负载，以便响应于代表二进制状态的输入信号被顺序地启动，以将输出驱动器耦合到负载。 输入信号通过预驱动级连接到相应的输出驱动级。 除了最低阶预驱动阶段之外，每个预驱动阶段都有一个使能电路，可在二进制状态之间的转换间隔内的所需点处接通驱动器级。

公开(公告)号：US5237213A

公开(公告)日：1993-08-17

申请号：US869257

申请日：1992-04-15

申请人： Satoru Tanoi

发明人： Satoru Tanoi

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K17/6872 ,  H03K17/167

摘要： A semiconductor integrated circuit has output buffers connected in parallel between one or more upper potential lines and one or more lower potential lines. Each output buffer has an output terminal coupled by first and third switching circuits to upper potential lines, and by second and fourth switching circuits to lower potential lines. In the high output state the first switching circuit is switched on, then the third switching circuit is switched on. In the low output state the second switching circuit is switched on, then the fourth switching circuit is switched on. An upper voltage threshold element switches the first switching circuit off above a first threshold output potential. A lower voltage threshold element switches the second circuit off below a second threshold output potential.

公开(公告)号：US4829199A

公开(公告)日：1989-05-09

申请号：US72831

申请日：1987-07-13

申请人： James S. Prater

发明人： James S. Prater

IPC分类号： G11C7/10 ,  H03K17/16 ,  H03K17/687

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K17/6872

摘要： A CMOS inverter driver circuit for powering an integrated circuit output pad or the like, capable of adapting by feedback detection to varying capacitive load conditions, and providing incrementally delayed current increases to avoid power supply and ground path spikes. In one configuration, a CMOS inventer is connected to an output pad, which output pad is further common to one or more pairs of complementary supplemental driver transistor stages. The supplemental driver stages are enabled by OR and AND local blocks responsive to the combinations of the input signal level and the output pad signal level. The supplemental driver stages are thereby enabled only during transient periods, when the output pad signal level is capacitively loaded and thereby held to a previous input state. Successive logic/delay stages between supplemental driver stages smoothes the composite output current waveform.

摘要翻译： 一种用于为集成电路输出焊盘等供电的CMOS反相器驱动器电路，其能够通过反馈检测适应于变化的容性负载条件，并且提供逐渐延迟的电流增加以避免电源和接地路径尖峰。 在一种配置中，CMOS发明者连接到输出焊盘，该输出焊盘对于一对或多对补充驱动晶体管级进一步共同。 辅助驱动器级由OR和AND本地块使能，响应于输入信号电平和输出焊盘信号电平的组合。 因此，当输出焊盘信号电平被电容加载并由此保持到先前的输入状态时，辅助驱动器级仅在瞬态期间被使能。 辅助驱动器级之间的连续逻辑/延迟级平滑复合输出电流波形。

公开(公告)号：US20240097672A1

公开(公告)日：2024-03-21

申请号：US17949454

申请日：2022-09-21

申请人： Apple Inc.

发明人： Yueming He ,  Dennis M. Fischette, JR.

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K17/167 ,  H03K19/00361

摘要： An integrated circuit may be provided with power switching circuitry. The power switching circuitry may include a primary power switch and multiple auxiliary power switches. A power gating control circuit may output control signals for selectively activating the primary power switch and at least one of the auxiliary power switches to charge a gated voltage. One or more voltage detectors may be configured to monitor the gated voltage and to activate the remaining auxiliary power switches in response to detecting that the gated voltage exceeds one or more thresholds. Configured and operated in this way, inrush current surge protection can be achieved while charging up the gated voltage sufficiently fast.

公开(公告)号：US11646733B2

公开(公告)日：2023-05-09

申请号：US17355427

申请日：2021-06-23

申请人： STMicroelectronics S.r.l.

发明人： Andrea Agnes

IPC分类号： H03K17/687 ,  H02J7/00 ,  H02M3/158 ,  H03K17/16

CPC分类号： H03K17/6872 ,  H02J7/007 ,  H02M3/158 ,  H03K17/167

摘要： In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

公开(公告)号：US20180062634A1

公开(公告)日：2018-03-01

申请号：US15247248

申请日：2016-08-25

申请人： TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.

发明人： Jongwon Shin

IPC分类号： H03K17/0814 ,  H03K17/041 ,  H03K17/90

CPC分类号： H03K17/167 ,  H03K17/04106 ,  H03K17/08142 ,  H03K17/0822 ,  H03K17/90

摘要： Methods, systems, and apparatus for eliminating gate voltage oscillation without increasing switching power loss in paralleled power semiconductor switches at high current turn-off. The damping circuit includes a switch for driving voltage and multiple resistors and multiple inductors. The damping circuit includes multiple capacitors connected to the multiple inductors. The damping circuit includes multiple power semiconductor switches that are connected to the multiple inductors at gate terminals. The damping circuit includes multiple gate terminal resistors connected in parallel to the multiple power semiconductor switches at the gate terminals and multiple gate terminal switches connected to the multiple gate terminal resistors.

公开(公告)号：US09800237B2

公开(公告)日：2017-10-24

申请号：US15117512

申请日：2015-03-12

申请人： DENSO CORPORATION

发明人： Sadahiro Akama ,  Kiyoshi Yamamoto ,  Atsushi Kobayashi ,  Atsushi Kanamori

IPC分类号： G05F1/565 ,  H03K17/567 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687

CPC分类号： H03K17/0406 ,  G05F1/565 ,  H03K17/167 ,  H03K17/567 ,  H03K17/6871

摘要： A drive device for controlling a power switching element includes: an on-side circuit that performs an on operation of the power switching element; and an off-side circuit that performs an off operation of the power switching element. The on-side circuit or the off-side circuit includes: multiple main MOS transistors; a sense MOS transistor that define a drain current of each main MOS transistor; and a sense current control circuit that controls a drain current of the sense MOS transistor to be constant; and a switch circuit that is connected to the gate of each main MOS transistor, and controls each main MOS transistor to turn on and off so as to switch a gate current in the power switching element.