公开(公告)号：US20210263661A1

公开(公告)日：2021-08-26

申请号：US17314493

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Robert N. Hasbun ,  Daniele Balluchi

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

公开(公告)号：US11074192B2

公开(公告)日：2021-07-27

申请号：US16655769

申请日：2019-10-17

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Dionisio Minopoli

IPC: G06F12/1009

Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

公开(公告)号：US20210208988A1

公开(公告)日：2021-07-08

申请号：US17206881

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20210191887A1

公开(公告)日：2021-06-24

申请号：US17192602

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Marco Dallabora ,  Daniele Balluchi ,  Paolo Amato ,  Luca Porzio

IPC: G06F13/16 ,  G06F13/28

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

公开(公告)号：US11036625B1

公开(公告)日：2021-06-15

申请号：US15929320

申请日：2020-04-24

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Dionisio Minopoli

IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0868

Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer write command requesting that data associated with a logical block address be written to the memory device and that a physical address to which the data is written be returned in response and performs a write operation to write the data associated with the logical block address to the physical address of the memory device. The processing device updates a translation layer entry corresponding to the logical block address to include the physical address and sends, to the host system, a response to the host-resident translation layer write command, the response comprising the updated translation layer entry with the physical address. The host system can to store the updated translation layer entry with the physical address in a host-resident translation layer mapping table.

公开(公告)号：US10943659B2

公开(公告)日：2021-03-09

申请号：US16744643

申请日：2020-01-16

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C11/00 ,  G11C13/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US10884661B2

公开(公告)日：2021-01-05

申请号：US16207453

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US20200319809A1

公开(公告)日：2020-10-08

申请号：US16905030

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Robert N. Hasbun ,  Daniele Balluchi

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

公开(公告)号：US10649665B2

公开(公告)日：2020-05-12

申请号：US15345919

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Marco Dallabora ,  Paolo Amato ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/00 ,  G11C13/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

公开(公告)号：US20200082900A1

公开(公告)日：2020-03-12

申请号：US16128113

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.