公开(公告)号：US20210257026A1

公开(公告)日：2021-08-19

申请号：US17191392

申请日：2021-03-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20210209458A1

公开(公告)日：2021-07-08

申请号：US17185725

申请日：2021-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  MARK REITEN

IPC: G06N3/063 ,  G06F17/16

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20210209456A1

公开(公告)日：2021-07-08

申请号：US16829757

申请日：2020-03-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G06F17/16 ,  G06F1/03

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US11031050B2

公开(公告)日：2021-06-08

申请号：US16526987

申请日：2019-07-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C7/06 ,  G11C7/02 ,  G11C16/28 ,  G11C11/56 ,  G11C16/04 ,  G11C5/14 ,  G11C11/4091 ,  G11C16/30

Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

公开(公告)号：US11011240B2

公开(公告)日：2021-05-18

申请号：US16879663

申请日：2020-05-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20210142854A1

公开(公告)日：2021-05-13

申请号：US17125459

申请日：2020-12-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/10 ,  G11C16/16 ,  G06N3/063

Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

公开(公告)号：US10861568B2

公开(公告)日：2020-12-08

申请号：US16590798

申请日：2019-10-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26 ,  G11C11/54

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US10860918B2

公开(公告)日：2020-12-08

申请号：US16182492

申请日：2018-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly

IPC: G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/08 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. The analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication arrays and various components shared by those arrays. The shared components include high voltage generation blocks, verify blocks, and testing blocks. The analog neuromorphic memory system optionally is used within a long short term memory system or a gated recurrent unit system.

公开(公告)号：US10803943B2

公开(公告)日：2020-10-13

申请号：US16382034

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  G11C11/34 ,  G06N3/063 ,  G06N3/08 ,  H01L29/788 ,  H01L27/11521 ,  G06N3/04 ,  H01L27/11517 ,  H01L29/423 ,  H01L27/11524 ,  H01L27/115 ,  G11C11/54

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

公开(公告)号：US10790022B2

公开(公告)日：2020-09-29

申请号：US16550254

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.