公开(公告)号：US20210098477A1

公开(公告)日：2021-04-01

申请号：US17121555

申请日：2020-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

公开(公告)号：US20210358551A1

公开(公告)日：2021-11-18

申请号：US17082956

申请日：2020-10-28

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STANLEY HONG ,  STEPHEN TRINH ,  THUAN VU ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

公开(公告)号：US20210295907A1

公开(公告)日：2021-09-23

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

公开(公告)号：US20240120009A1

公开(公告)日：2024-04-11

申请号：US18530832

申请日：2023-12-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  Mark REITEN

IPC: G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54

CPC classification number: G11C16/10 ,  G06F17/16 ,  G06N3/0442 ,  G06N3/063 ,  G11C11/54 ,  G11C2216/04

Abstract: In one example, a method comprises applying a first programming pulse to a terminal of a selected non-volatile memory cell; and applying a second programming pulse to the terminal of the selected non-volatile memory cell, wherein a magnitude of a voltage the second programming pulse is equal to or lower than a magnitude of a voltage of the first programming pulse; wherein the selected non-volatile memory cell is programmed to a target value by the first programming pulse and the second programming pulse.

公开(公告)号：US20220336010A1

公开(公告)日：2022-10-20

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20210209458A1

公开(公告)日：2021-07-08

申请号：US17185725

申请日：2021-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  MARK REITEN

IPC: G06N3/063 ,  G06F17/16

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20220383086A1

公开(公告)日：2022-12-01

申请号：US17875167

申请日：2022-07-27

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: G06N3/063 ,  G06F17/16 ,  G11C11/54 ,  G11C11/56

Abstract: Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a method for performing a read or verify operation in a vector-by-matrix multiplication system comprising an input function circuit, a memory array, and an output circuit block is disclosed, the method comprising receiving, by the input function circuit, digital bit input values; converting the digital input values into an input signal; applying the input signal to control gate terminals of selected cells in the memory array; and generating, by the output circuit block, an output value in response to currents received from the memory array.

公开(公告)号：US20220336011A1

公开(公告)日：2022-10-20

申请号：US17857113

申请日：2022-07-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

公开(公告)号：US20200350015A1

公开(公告)日：2020-11-05

申请号：US16930777

申请日：2020-07-16

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEVEN LEMKE ,  NHAN DO ,  VIPIN TIWARI ,  MARK REITEN

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

公开(公告)号：US20240274187A1

公开(公告)日：2024-08-15

申请号：US18645018

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.