Abstract:
An aggregation channel for providing data communication for M data streams to N data streams comprises a first first-in, first-out (FIFO) buffer module that receives the M data streams and realigns them with each other based on respective alignment symbols. A lane mapping module receives the realigned M data streams from the first FIFO buffer module and routes predetermined ones of the M data streams to predetermined ones of the N data streams, wherein each of the N data streams receives at least one of the alignment characters. M is greater than N, N is greater than 1, and each of the M data streams includes an alignment symbol.
Abstract:
A system for probing a DUT is disclosed, the system having a pulsed laser source, a CW laser source, beam optics designed to point a reference beam and a probing beam at the same location on the DUT, optical detectors for detecting the reflected reference and probing beams, and a collection electronics. The beam optics is a common-path polarization differential probing (PDP) optics. The common-path PDP optics divides the incident laser beam into two beams of orthogonal polarization—one beam simulating a reference beam while the other simulating a probing beam. Both reference and probing beams are pointed to the same location on the DUT. Due to the intrinsic asymmetry of a CMOS transistor, the interaction of the reference and probing beams with the DUT result in different phase modulation in each beam. This difference can be investigated to study the response of the DUT to the stimulus signal.
Abstract:
A physical coding sublayer (PCS) device includes a first data scrambler, a second data scrambler, and a selector. The first data scrambler scrambles first data and implements a first scrambling cycle. The second data scrambler scrambles second data and implements a second scrambling cycle. The second data is different than the first data. The second scrambling cycle is shorter than the first scrambling cycle. The selector selects the first data scrambler to scramble the first data during normal operations. The selector selects the second data scrambler to scramble the second data during testing. The first data scrambler does not scramble the second data. The second data scrambler does not scramble the first data.
Abstract:
An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EERPOMs is written to registers in the physical layer device to configure the physical layer device.
Abstract:
A method for communicating network data of varying speeds comprises establishing a plurality of signal interconnections; storing a first mapping of XGMII signals onto the plurality of signal interconnections; storing a second mapping of GMII signals onto the plurality of signal interconnections; and storing a third mapping of MII signals onto the plurality of signal interconnections. Ones of the plurality of signal interconnections are mapped by each of the first, second, and third mappings. The method further comprises selecting one of the first, second, and third mappings and transmitting the network data over the plurality of signal interconnections using the selected one of the first, second, and third mappings.
Abstract:
A physical-layer device (PHY) having corresponding methods comprises: a data rate module to select a data rate divisor N, where N is at least one of a positive integer, or a real number greater than, or equal to, 1; and a PHY core comprising a PHY transmit module to transmit first signals a data rate of M/N Gbps, and a PHY receive module to receive second signals at the data rate of MIN Gbps; wherein the first and second signals conform to at least one of 1000BASE-T, wherein M=1, and 10GBASE-T, wherein M=10.
Abstract:
A network device that operates in first and second serial gigabit interface modes involving data speed translation comprising a medium access control (MAC) device that transmits idle order sets. A physical layer (PHY) device receives the idle order sets and that switches from the first serial gigabit interface mode to the second serial gigabit interface mode if a first predetermined number of consecutive idle order sets are equal to a first idle order set.
Abstract:
A medium access control (MAC) device comprising an encoder that encodes a transmit control signal including one of a transmit enable signal in one half cycle of a clock signal and a transmit error signal in another half cycle of the clock signal. A control signal transmitter transmits the encoded transmit control signal. A data signal transmitter selectively transmits a transmit data signal including signaling data based on states of the transmit enable signal and the transmit error signal during the clock cycle.
Abstract:
A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually.
Abstract:
Apparatus having corresponding methods and computer programs comprise a first first-in first-out buffer (FIFO) to receive and store data from a media access controller (MAC); a physical-layer device (PHY) to transmit a signal representing the data; and a control circuit comprising a read circuit to transfer the data from the first FIFO to the PHY, and a transmit pause circuit to transmit a pause frame to the MAC when an amount of the data stored in the first FIFO exceeds a predetermined threshold.