公开(公告)号：US20080219356A1

公开(公告)日：2008-09-11

申请号：US12042300

申请日：2008-03-04

Applicant: Sumit Johar ,  Ravin Sachdeva

Inventor： Sumit Johar ,  Ravin Sachdeva

IPC: H04N7/24

CPC classification number: H04N19/00472 ,  H04N19/40 ,  H04N19/61

Abstract: A system and method transcodes an input video bit stream having a first encoding profile into an output video bit stream having a second encoding profile. The system includes a first module (302) and a second module (306). The system further includes a memory module (304). The first module (302) decodes the input video bit stream for generating pixel data and macroblock specifications. The second module (306) encodes the pixel data and the macroblock specifications for constructing the output video bit stream. The memory module (304) includes a first buffer module and a second buffer module. The first buffer module stores the pixel data and the second buffer module stores the macroblock specifications.

Abstract translation: 系统和方法将具有第一编码简档的输入视频比特流转码成具有第二编码简档的输出视频比特流。 该系统包括第一模块（302）和第二模块（306）。 该系统还包括存储器模块（304）。 第一模块（302）解码用于产生像素数据和宏块规格的输入视频比特流。 第二模块（306）对构成输出视频比特流的像素数据和宏块规格进行编码。 存储器模块（304）包括第一缓冲器模块和第二缓冲器模块。 第一缓冲模块存储像素数据，第二缓存模块存储宏块规格。

公开(公告)号：US20080218151A1

公开(公告)日：2008-09-11

申请号：US11964127

申请日：2007-12-26

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: G01R19/00

CPC classification number: G01R29/023 ,  G01R31/31727

Abstract: A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage. The duty cycle for the second clock signal is then calculated using the first elapsed cycle and the second elapsed cycle.

Abstract translation: 一种用于测量片上占空比的方法和电路。 该电路包括电容器，开关电路，电流源，比较器电路和计数器。 电路接收第一时钟信号和第二时钟信号。 第一个时钟信号占空比为50％，第二个信号具有未知的占空比信号。 开关电路首先接收第一时钟信号，然后接收用于测量占空比的第二时钟信号。 比较器电路将比较器电压与第一时钟信号的参考电压进行比较，以使用计数器测量第一次经过的周期。 比较器电路再次将比较器电压与第二时钟信号的参考电压进行比较，以使用计数器测量第二个经过的周期。 在比较器电压等于参考电压的持续时间内，计数器测量对应于第一时钟信号和第二时钟信号的第一经过周期和第二经过周期。 然后使用第一经过循环和第二经过循环来计算第二时钟信号的占空比。

公开(公告)号：US20080144401A1

公开(公告)日：2008-06-19

申请号：US11616499

申请日：2006-12-27

Applicant: Nasim Ahmad

Inventor： Nasim Ahmad

IPC: G11C7/06

CPC classification number: G11C7/22 ,  G11C7/08 ,  G11C7/227

Abstract: A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block with a dummy bit line connected to the dummy column and to a timing circuit. A normal bit line connected to the normal memory cells provides the read normal bit to input/output logic. Whenever a normal memory cell is accessed during the read operation, the circuitry of the corresponding dummy row enables the dummy bit line to discharge, and when the voltage across the dummy bit line reaches a predetermined value, the timing circuit produces a timing signal to activate the input/output circuitry to read the data stored in the accessed memory cell.

Abstract translation: 一种半导体存储器件，其具有控制电路，解码器电路，虚拟列和正常存储单元阵列，其以N个连续行的簇分割，其中N可以是一个或多于一个，并且对于N行的每个簇，公共电路 被用于具有连接到虚拟列和定时电路的虚拟位线的块中。 连接到正常存储单元的正常位线将读取正常位提供给输入/输出逻辑。 无论何时在读取操作期间访问正常存储器单元时，相应虚拟行的电路使得虚拟位线能够放电，并且当虚拟位线两端的电压达到预定值时，定时电路产生定时信号以激活 输入/输出电路读取存储在存取存储单元中的数据。

公开(公告)号：US20080143390A1

公开(公告)日：2008-06-19

申请号：US11861924

申请日：2007-09-26

Applicant: Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Ankur Goel ,  Mudit Bhargava ,  Shishir Kumar

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/413

Abstract: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage. The amplifier further includes a pull down circuit and a delay circuit. The delay circuit produces delay between two control signals. The circuit includes a first NOT gate and a second NOT gate operatively coupled to a first latch output node and a second latch output node respectively to provide an output data corresponding to a data stored in a memory cell.

Abstract translation: 读出放大器电路提供具有低电容和低分辨率时间的高速读取操作的高速感测。 读出放大器电路包括具有彼此交叉耦合的第一反相器电路和第二反相器电路的锁存电路。 放大器电路包括分别可操作地耦合到第一反相器电路和第二反相器电路的第一放电装置和第二放电装置。 放大器电路还包括可操作地耦合在第一放电器件和位线之间的第一PMOS晶体管和可操作地耦合在第二放电器件和互补位线之间的第二PMOS晶体管。 放大器电路还包括可操作地耦合在第一放电装置和接地电压之间的第一NMOS晶体管，可操作地耦合在第二放电装置和接地电压之间的第二NMOS晶体管。 放大器还包括下拉电路和延迟电路。 延迟电路在两个控制信号之间产生延迟。 电路包括分别操作地耦合到第一锁存器输出节点和第二锁存器输出节点的第一NOT门和第二NOT门，以提供对应于存储在存储器单元中的数据的输出数据。

公开(公告)号：US07380187B2

公开(公告)日：2008-05-27

申请号：US11024946

申请日：2004-12-29

Applicant: Rohit Dubey

Inventor： Rohit Dubey

IPC: G01R31/317 ,  G01R31/40

CPC classification number: G01R31/318547

Abstract: A boundary scan tester is provided for testing logic devices. The boundary scan tester includes a boundary scan register, a data decompressor, a data compressor, and a derived boundary scan register. The boundary scan register registers the applied test vectors and test responses of a logic device, and the data decompressor is coupled to an input of the boundary scan register for decompressing the applied compressed test vectors. The data compressor is coupled to an output of the boundary scan register for compressing the test responses, and the derived boundary scan register is coupled to an input of the decompressor and an output of the compressor for storing and shifting in/out the compressed test vectors and test responses.

Abstract translation: 提供边界扫描测试仪用于测试逻辑器件。 边界扫描测试仪包括边界扫描寄存器，数据解压缩器，数据压缩器和派生的边界扫描寄存器。 边界扫描寄存器注册应用的测试向量和测试逻辑器件的响应，并且数据解压缩器耦合到边界扫描寄存器的输入端，用于解压缩所应用的压缩测试向量。 数据压缩器耦合到边界扫描寄存器的输出端，用于压缩测试响应，导出的边界扫描寄存器耦合到解压缩器的输入端和压缩器的输出端，用于存储和移入/输出压缩的测试向量 并测试回应。

公开(公告)号：US07372764B2

公开(公告)日：2008-05-13

申请号：US11200867

申请日：2005-08-10

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: A logic device operates with reduced leakage current. Controllability is achieved by using a reference voltage to control the amount of leakage reduction. A method of temperature dependent reference voltage generation is given which maintains virtual supply in acceptable range to provide sufficient noise margin in logic devices including memory cells.

Abstract translation: 逻辑器件以减少的漏电流工作。 通过使用参考电压来控制泄漏量的减少来实现可控性。 给出了一种依赖于温度的参考电压产生方法，其将虚拟电源维持在可接受的范围内，以在包括存储器单元的逻辑器件中提供足够的噪声

公开(公告)号：US20080074189A1

公开(公告)日：2008-03-27

申请号：US11900928

申请日：2007-09-12

Applicant: Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik

Inventor： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik

IPC: H03F3/45

CPC classification number: H03F3/45659 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45434 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

Abstract translation: 连续时间共模反馈模块能够在宽范围的输入电压下工作。 共模反馈模块包括共模检测器和用于计算和放大第一输入信号和第二输入信号的参考电压和共模电压的差的放大器。 共模反馈模块包括共模分解器和彼此耦合以提供共模反馈电压的控制电压产生模块。 共模反馈模块提供良好的线性度和宽带宽，无需补偿要求。 共模反馈模块还提供偏置电流和共模偏移的小过程角依赖性。

公开(公告)号：US20080074148A1

公开(公告)日：2008-03-27

申请号：US11895643

申请日：2007-08-23

Applicant: Ankit Srivastava ,  Sourav Jandial

Inventor： Ankit Srivastava ,  Sourav Jandial

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/018528 ,  H03K3/012 ,  H03K3/356165 ,  H03K3/356182

Abstract: Embodiments of the present invention provide level shifter circuits capable of high frequency operations. The level shifter circuit utilizes a dynamic charge injection device, which diminishes a capacitive coupling effect between a gate and a drain of input NMOS devices, when the input signal switches from a high logic level to a low logic level. The dynamic charge injection device is incorporated at output nodes to provide initial thrust to the level shifter circuits, which triggers a positive regenerative feedback of cross-coupled pull up PMOS devices enabling a rapid transition and hence the high frequency operation.

Abstract translation: 本发明的实施例提供能够进行高频操作的电平移位电路。 当输入信号从高逻辑电平切换到低逻辑电平时，电平移位器电路利用动态电荷注入器件，其减小输入NMOS器件的栅极和漏极之间的电容耦合效应。 动态电荷注入装置并入输出节点以向电平移位器电路提供初始推力，这触发了交叉耦合上拉PMOS器件的正再生反馈，从而实现快速转换，从而实现高频操作。

公开(公告)号：US20080068512A1

公开(公告)日：2008-03-20

申请号：US11841678

申请日：2007-08-20

Applicant: Vivek Sharma ,  Sheetal Jain

Inventor： Vivek Sharma ,  Sheetal Jain

IPC: H04N5/40

CPC classification number: H04N21/2368 ,  H04N5/40 ,  H04N21/2383

Abstract: A digital radio frequency (RF) modulator provides modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analog up conversion. The RF modulator includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/− 13.5 MHz. The RF interpolator includes a zero pad logic followed by a quadrature band pass filter (BPF), and an optional second stage of another zero-pad logic followed by a real band pass filter (BPF). The second stage is optional in the sense that it is required only if the desired RF channel is in the higher VHF band.

Abstract translation: 数字射频（RF）调制器为基带电视信号提供调制。 RF调制器可将数字基带音频和视频信号直接转换为所需的RF信道频率，无需任何模拟上变频。 RF调制器包括音频模块，视频模块和RF转换器。 音频模块包括预加重滤波器，多级音频插值器和复频调制器，以产生调频（FM）音频信号。 视频模块包括复合VSB滤波器，组延迟补偿滤波器和用于产生经滤波的输出视频信号的一些处理逻辑。 RF转换器包括复数加法器，复数乘法器和RF插值器，用于构造基带TV信号并将频域中的基带TV信号移位到期望的RF信道频率。 指数视频载波在基带处产生，其频率范围为+/- 13.5MHz。 RF内插器包括跟随有正交带通滤波器（BPF）的零焊盘逻辑，以及随后是实数带通滤波器（BPF）的另一零焊盘逻辑的可选的第二级。 在第二阶段是可选的，只有当所需的RF信道处于较高VHF频带时才需要。

公开(公告)号：US20080059690A1

公开(公告)日：2008-03-06

申请号：US11724046

申请日：2007-03-14

Applicant: Alok Mittal ,  Hubert Rousseau ,  Rosarium Pila

Inventor： Alok Mittal ,  Hubert Rousseau ,  Rosarium Pila

IPC: G06F12/06

CPC classification number: G06F13/1694

Abstract: A system and method of making a firmware self updatable depending on option information stored in a configuration module. The configuration module can either be in a memory device or a memory controller. The self-updation flexibility can be achieved by customizing the options as per the customer's requirements and can be done either through an USB interface or by pre-programming the configuration module or any other communication or programming options. The option information is provided by using a configurable module inside either the memory or the memory controller. After the basic initialization operations, the firmware reads the option information from the controller itself or any other non-volatile memory and performs the tasks to enhance the overall performance.

Abstract translation: 根据存储在配置模块中的选项信息，使固件可自行更新的系统和方法。 配置模块可以在存储设备或存储器控制器中。 可以通过根据客户要求定制选项来实现自动更新灵活性，并且可以通过USB接口或通过预配置模块或任何其他通信或编程选项进行编程。 选项信息通过在存储器或存储器控制器内部使用可配置模块来提供。 在基本初始化操作之后，固件从控制器本身或任何其他非易失性存储器读取选项信息，并执行任务以增强整体性能。