公开(公告)号：US20110115536A1

公开(公告)日：2011-05-19

申请号：US12938155

申请日：2010-11-02

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03L7/06

CPC classification number: H03L7/0816 ,  H03M1/0836 ,  H03M1/145 ,  H03M1/164 ,  H03M1/44

Abstract: In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).

Abstract translation: 在传统的模数转换器（ADC）系统中，由于采样信号路径内的延迟电路，抖动可能是一个问题。 这里，ADC系统具有修改的延迟锁定环（DLL），即具有可变延迟和固定延迟。 对DLL的延迟线的修改使得能够从采样路径去除延迟电路，从而提高整体信噪比（SNR）。

公开(公告)号：US07795958B2

公开(公告)日：2010-09-14

申请号：US12177170

申请日：2008-07-22

Applicant: Nitin Agarwal ,  Saurabh Singh

Inventor： Nitin Agarwal ,  Saurabh Singh

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45475 ,  H03F3/45928 ,  H03F2203/45101 ,  H03F2203/45586 ,  H03F2203/45588

Abstract: A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of different cycles in an input path of a switched capacitor differential amplifier. In an embodiment, for each hold phase, the reference generator provides the reference potential with a magnitude that tracks the magnitude of the input signal applied in a corresponding (preceding) sample phase. In case of a single-ended output, the reference potential generated for each hold phase equals the magnitude of one of the inputs on the differential input path. As a result, the common mode voltage at the input terminals of an operational amplifier contained in the switched capacitor differential amplifier is maintained at a desired level.

Abstract translation: 根据本发明的一方面提供的参考生成电路在开关电容差分放大器的输入路径中的不同周期的保持相位中产生不同电平的参考电位。 在一个实施例中，对于每个保持相位，参考发生器提供具有跟踪在相应的（在前）采样相位中施加的输入信号的幅度的幅度的参考电位。 在单端输出的情况下，为每个保持相产生的参考电位等于差分输入路径上的一个输入的幅度。 结果，包含在开关电容差分放大器中的运算放大器的输入端的共模电压保持在期望的水平。

公开(公告)号：US20100019841A1

公开(公告)日：2010-01-28

申请号：US12177170

申请日：2008-07-22

Applicant: Nitin Agarwal ,  Saurabh Singh

Inventor： Nitin Agarwal ,  Saurabh Singh

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45475 ,  H03F3/45928 ,  H03F2203/45101 ,  H03F2203/45586 ,  H03F2203/45588

Abstract: A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of different cycles in an input path of a switched capacitor differential amplifier. In an embodiment, for each hold phase, the reference generator provides the reference potential with a magnitude that tracks the magnitude of the input signal applied in a corresponding (preceding) sample phase. In case of a single-ended output, the reference potential generated for each hold phase equals the magnitude of one of the inputs on the differential input path. As a result, the common mode voltage at the input terminals of an operational amplifier contained in the switched capacitor differential amplifier is maintained at a desired level.

Abstract translation: 根据本发明的一方面提供的参考生成电路在开关电容差分放大器的输入路径中的不同周期的保持相位中产生不同电平的参考电位。 在一个实施例中，对于每个保持相位，参考发生器提供具有跟踪在相应的（在前）采样相位中施加的输入信号的幅度的幅度的参考电位。 在单端输出的情况下，为每个保持相产生的参考电位等于差分输入路径上的一个输入的幅度。 结果，包含在开关电容差分放大器中的运算放大器的输入端的共模电压保持在期望的水平。

公开(公告)号：US20090315594A1

公开(公告)日：2009-12-24

申请号：US12199804

申请日：2008-08-28

Applicant: Visvesvaraya Appala Pentakota ,  Nitin Agarwal

Inventor： Visvesvaraya Appala Pentakota ,  Nitin Agarwal

IPC: H03K3/00

CPC classification number: H03M1/124 ,  H03F3/505 ,  H03F2200/312 ,  H03F2203/5031

Abstract: A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.

Abstract translation: 根据本发明的一方面提供的源极跟随器或射极跟随器缓冲器包括连接在输入路径和由形成连接到缓冲器的输出的级联电流源的一对晶体管的结的形成的节点之间的电容器。 电容器将输入信号电流直接传递到连接到缓冲器输出的开关负载，并且极少的信号相关电流流过接收输入信号的晶体管。 结果，由于接收输入信号的晶体管的跨导的信号相关调制（变化）引起的输入 - 输出非线性被最小化。 当结合在开关电容器模数转换器中时，缓冲器便于更准确地产生代表输入信号的数字代码。

公开(公告)号：US07598816B2

公开(公告)日：2009-10-06

申请号：US11638306

申请日：2006-12-12

Applicant: Nitin Agarwal ,  Kallol Chatterjee

Inventor： Nitin Agarwal ,  Kallol Chatterjee

IPC: H03L7/08

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.

Abstract translation: 锁相环（PLL）电路包括用于防止电荷泵操作中的错误状况的电路。 通过添加用于相位频率检测器和电荷泵之间的连接的延迟元件来修改PLL电路。 还包括数字逻辑电路以提供用于环路滤波器的时钟信号，其中时钟信号具有对应于来自相位 - 频率检测器的任一个输出信号的较早出现的上升沿的上升沿。

公开(公告)号：US20090135037A1

公开(公告)日：2009-05-28

申请号：US11945278

申请日：2007-11-27

Applicant: Nitin Agarwal ,  Ramesh Kumar Singh ,  Visvesvaraya A. Pentakota ,  Dantes John ,  Supreet Joshi

Inventor： Nitin Agarwal ,  Ramesh Kumar Singh ,  Visvesvaraya A. Pentakota ,  Dantes John ,  Supreet Joshi

IPC: H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/0624 ,  H03M1/167 ,  H03M1/362

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Abstract translation: 偏移校正电路检查管线模数转换器（ADC）的级的残留信号，以确定是否需要调整可能导致偏移误差的参数。 在一个实施例中，调整参数直到残差信号的最大范围等于预期范围。 在所描述的示例中，经调整的参数包括定时偏移误差（当ADC的分量对不同时间的输入信号进行采样时）和电压偏移误差（在产生子码的阶段中的子ADC的阈值电压 更改为下一个值）。

公开(公告)号：US20080018369A1

公开(公告)日：2008-01-24

申请号：US11649747

申请日：2007-01-03

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L1/022 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract translation: 锁相环（PLL）架构提供跨工艺和温度的压控振荡器（VCO）增益补偿。 可以使用模拟器来计算用于处理和温度转角的每个组合的VCO的最大和最小输出频率的控制电压。 然后从这些控制电压中选择控制电压的最大值和最小值。 使用计数器，在PLL输入时钟的一些周期中，VCO的周期数以二进制形式计数，并存储在用于极端控制电压的锁存器中。 它们之间的差异与典型工艺和温度角的相应差异用于修改电荷泵以改变递送到环路滤波器的电流。 电荷泵位决定后，VCO的输入控制电压连接到电荷泵输出，开始PLL的正常工作。

公开(公告)号：US20050099217A1

公开(公告)日：2005-05-12

申请号：US10704210

申请日：2003-11-06

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: G06F1/08 ,  H03K3/017

CPC classification number: G06F1/08

Abstract: A method and system for generating variable frequency cyclic waveforms using pulse width modulation (PWM) to provide adjustable precision frequency and enhanced resolution is disclosed. The technique includes a plurality of sets of duty cycle values, each set corresponding to the desired waveform profile at a given frequency, coupled with a mechanism for applying a selected duty cycle for a variable number of PWM cycles, to achieve an adjustable fine resolution of the waveform frequency.

Abstract translation: 公开了一种使用脉宽调制（PWM）产生可变频率循环波形以提供可调精度频率和增强分辨率的方法和系统。 该技术包括多个工作周期值集合，每个集合对应于给定频率处的期望波形分布，以及用于对可变数量的PWM周期施加所选择的占空比的机制，以实现可调节的精细分辨率 波形频率。

公开(公告)号：US11669831B2

公开(公告)日：2023-06-06

申请号：US17224300

申请日：2021-04-07

Applicant: Miles Paschini ,  Nitin Agarwal

Inventor： Miles Paschini ,  Nitin Agarwal

IPC: G06Q20/36 ,  H04L9/06 ,  G06Q20/40

CPC classification number: G06Q20/3672 ,  G06Q20/3674 ,  G06Q20/3678 ,  G06Q20/4016 ,  H04L9/0637

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

公开(公告)号：US08581634B2

公开(公告)日：2013-11-12

申请号：US12763945

申请日：2010-04-20

Applicant: Nitin Agarwal ,  Visvesvaraya A. Pentakota

Inventor： Nitin Agarwal ,  Visvesvaraya A. Pentakota

IPC: G11C27/02

CPC classification number: H03K19/018528 ,  G11C27/024

Abstract: Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved.

Abstract translation: 传统上，模数转换器（ADC）的输入源跟随缓冲器缺乏足够高的线性度。 这是由于源极跟随缓冲器必须通过向容性负载提供信号电流来驱动外部电容性负载。 这里提供了缓冲器，其包括源极跟随器缓冲器和其它偏置电路（其提供信号电流）。 因此，输入电路（即，输入缓冲器）的整体线性度得到改善。