MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS

    公开(公告)号:US20210111154A1

    公开(公告)日:2021-04-15

    申请号:US17128558

    申请日:2020-12-21

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

    MICROELECTRONIC ASSEMBLIES
    173.
    发明申请

    公开(公告)号:US20200286871A1

    公开(公告)日:2020-09-10

    申请号:US16650698

    申请日:2017-12-29

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die.

    MICROELECTRONIC ASSEMBLIES
    174.
    发明申请

    公开(公告)号:US20200279829A1

    公开(公告)日:2020-09-03

    申请号:US16649949

    申请日:2017-12-29

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a transmitter/receiver logic (TRL) die coupled to the first surface of the package substrate; a plurality of antenna elements adjacent the second surface of the package substrate; and a transmitter/receiver chain (TRC) die, wherein the TRC die is embedded in the package substrate, and wherein the TRC die is electrically coupled to the RF die and at least one of the plurality of antenna elements via conductive pathways in the package substrate. In some embodiments, a microelectronic assembly may further include a double-sided TRC die. In some embodiments, a microelectronic assembly may further include a TRC die having an amplifier. In some embodiments, a microelectronic assembly may further include a TRL die having a modem and a phase shifter.

    MICROELECTRONIC ASSEMBLIES WITH COMMUNICATION NETWORKS

    公开(公告)号:US20200273840A1

    公开(公告)日:2020-08-27

    申请号:US16648464

    申请日:2017-12-29

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

    MICROELECTRONIC ASSEMBLIES
    177.
    发明申请

    公开(公告)号:US20200227401A1

    公开(公告)日:2020-07-16

    申请号:US16650499

    申请日:2017-12-29

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

    Waveguide connector with tapered slot launcher

    公开(公告)号:US10566672B2

    公开(公告)日:2020-02-18

    申请号:US15277504

    申请日:2016-09-27

    Abstract: The systems and methods described herein provide a traveling wave launcher system physically and communicably coupled to a semiconductor package and to a waveguide connector. The traveling wave launcher system includes a slot-line signal converter and a tapered slot launcher. The slot-line signal converter may be formed integral with the semiconductor package and includes a balun structure that converts the microstrip signal to a slot-line signal. The tapered slot launcher is communicably coupled to the slot-line signal converter and includes a planar first member and a planar second member that form a slot. The tapered slot launcher converts the slot-line signal to a traveling wave signal that is propagated to the waveguide connector.

    MICROELECTRONIC ASSEMBLIES
    180.
    发明申请

    公开(公告)号:US20190385977A1

    公开(公告)日:2019-12-19

    申请号:US16008879

    申请日:2018-06-14

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

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