公开(公告)号：US10734333B2

公开(公告)日：2020-08-04

申请号：US16093828

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard Lincoln Heck

IPC: H01L23/42 ,  H01L23/52 ,  H01L29/40 ,  H01L23/66 ,  H01L23/498 ,  H01L23/525 ,  H01L21/48 ,  H01L23/64 ,  H01L23/31

Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.

公开(公告)号：US10734318B2

公开(公告)日：2020-08-04

申请号：US16018635

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Yun Rou Lim

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538

Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.

公开(公告)号：US20200168559A1

公开(公告)日：2020-05-28

申请号：US16663853

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

公开(公告)号：US20200168538A1

公开(公告)日：2020-05-28

申请号：US16662990

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L23/495 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: An embedded interconnect bridge includes a backside trace that can be coupled to a power plane within a semiconductor package substrate. The embedded interconnect bridge-backside trace preserves useful package real estate that is near to where multiple dice are to be mounted on the semiconductor package substrate.

公开(公告)号：US10651127B2

公开(公告)日：2020-05-12

申请号：US15845382

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Paik Wen Ong

IPC: H01L23/50 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L25/16 ,  H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H01L25/00 ,  H01L23/64 ,  H01L25/065

Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US20200083194A1

公开(公告)日：2020-03-12

申请号：US16473570

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Ping Ping Ooi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.

公开(公告)号：US10580761B2

公开(公告)日：2020-03-03

申请号：US16019023

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Boon Ping Koh ,  Kooi Chi Ooi

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/00 ,  H01Q21/22 ,  H01Q1/52 ,  H01Q21/00 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L23/538

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

公开(公告)号：US20200043831A1

公开(公告)日：2020-02-06

申请号：US16402482

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20200006247A1

公开(公告)日：2020-01-02

申请号：US16423561

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/552 ,  H01L23/522

Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.

公开(公告)号：US20190393141A1

公开(公告)日：2019-12-26

申请号：US16402553

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/498 ,  H01L23/66 ,  H01L25/18 ,  H01L23/552 ,  H01L23/00

Abstract: Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.