-
公开(公告)号：US11277903B2
公开(公告)日：2022-03-15
申请号：US16368221
申请日：2019-03-28
申请人： Intel Corporation
IPC分类号： H05K3/02 , H05K1/02 , G05B19/4097 , H05K1/18
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
-
公开(公告)号：US20190008029A1
公开(公告)日：2019-01-03
申请号：US16021618
申请日：2018-06-28
申请人： Intel Corporation
发明人： Khang Choong Yong , Bok Eng Cheah , Jackson Chung Peng Kong , Stephen Harvey Hall , Yun Rou Lim
IPC分类号： H05K1/02 , H01L23/498 , H01L23/64
摘要： Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.
-
公开(公告)号：US11729900B2
公开(公告)日：2023-08-15
申请号：US17694201
申请日：2022-03-14
申请人： Intel Corporation
IPC分类号： H05K1/02 , G05B19/4097 , H05K3/02 , H05K1/18
CPC分类号： H05K1/0225 , G05B19/4097 , H05K3/027 , G05B2219/45026 , G05B2219/45034 , H05K1/18 , H05K2201/093 , H05K2201/098 , H05K2201/09027 , H05K2201/10098
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
-
公开(公告)号：US10484231B2
公开(公告)日：2019-11-19
申请号：US16021292
申请日：2018-06-28
申请人： Intel Corporation
发明人： Khang Choong Yong , Bok Eng Cheah , Jackson Chung Peng Kong , Stephen Harvey Hall , Yun Rou Lim
摘要： Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.
-
公开(公告)号：US20190007259A1
公开(公告)日：2019-01-03
申请号：US16021292
申请日：2018-06-28
申请人： Intel Corporation
发明人： Khang Choong Yong , Bok Eng Cheah , Jackson Chung Peng Kong , Stephen Harvey Hall , Yun Rou Lim
CPC分类号： H04L29/10 , H01R13/6658 , H01R13/6691 , H05K1/025 , H05K1/0251 , H05K2201/09345 , H05K2201/09727
摘要： Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.
-
公开(公告)号：US20220304143A1
公开(公告)日：2022-09-22
申请号：US17694201
申请日：2022-03-14
申请人： Intel Corporation
IPC分类号： H05K1/02 , G05B19/4097 , H05K3/02
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
-
公开(公告)号：US11955436B2
公开(公告)日：2024-04-09
申请号：US16393304
申请日：2019-04-24
申请人： Intel Corporation
发明人： Khang Choong Yong , Ying Ern Ho , Yun Rou Lim , Wil Choon Song , Stephen Hall
IPC分类号： H01L23/552 , H01L23/00 , H01L23/66 , H05K1/02
CPC分类号： H01L23/552 , H01L23/66 , H01L24/17 , H05K1/0216 , H05K1/025 , H01L2223/6627
摘要： Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
-
公开(公告)号：US10856407B2
公开(公告)日：2020-12-01
申请号：US16021618
申请日：2018-06-28
申请人： Intel Corporation
发明人： Khang Choong Yong , Bok Eng Cheah , Jackson Chung Peng Kong , Stephen Harvey Hall , Yun Rou Lim
摘要： Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.
-
公开(公告)号：US10734318B2
公开(公告)日：2020-08-04
申请号：US16018635
申请日：2018-06-26
申请人： Intel Corporation
IPC分类号： H01L23/49 , H01L23/498 , H01L23/00 , H01L21/768 , H01L23/538
摘要： A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.012 秒)
