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    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE
    172.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE 审中-公开

    公开(公告)号：US20230269922A1

    公开(公告)日：2023-08-24

    申请号：US18141046

    申请日：2023-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H10B12/00 ,  G11C11/401

    CPC classification number: H10B12/20 ,  G11C11/401

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY
    174.
    发明申请
    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY 有权

    公开(公告)号：US20230138620A1

    公开(公告)日：2023-05-04

    申请号：US17515782

    申请日：2021-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Litao Yang ,  Kamal M. Karda

    IPC: H01L27/11551 ,  H01L21/8234 ,  H01L21/02

    Abstract: Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has serially connected horizontally oriented transistors each having an independent first source/drain region and a shared second source/drain region separated by channel regions, and gates opposing the channel regions and separated therefrom by a gate dielectric;
    pairs of vertically oriented access lines coupled to the gates and separated from the channel region by the gate dielectric; and horizontally oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented transistors.

    Self-aligned etch back for vertical three dimensional (3D) memory
    176.
    发明授权
    Self-aligned etch back for vertical three dimensional (3D) memory 有权

    公开(公告)号：US11641732B2

    公开(公告)日：2023-05-02

    申请号：US17237664

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Si-Woo Lee ,  Haitao Liu ,  Kamal M. Karda

    IPC: H01L27/108 ,  H01L27/11507 ,  H01L27/11514

    Abstract: Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

    Vertical 3D single word line gain cell with shared read/write bit line
    177.
    发明授权
    Vertical 3D single word line gain cell with shared read/write bit line 有权

    公开(公告)号：US11631453B2

    公开(公告)日：2023-04-18

    申请号：US17545756

    申请日：2021-12-08

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/00 ,  G11C11/4097 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SEPARATE READ AND WRITE CONTROL GATES
    179.
    发明申请
    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SEPARATE READ AND WRITE CONTROL GATES 有权

    公开(公告)号：US20230031362A1

    公开(公告)日：2023-02-02

    申请号：US17387669

    申请日：2021-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

    IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/28

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGION
    180.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGION 有权

    公开(公告)号：US20230030585A1

    公开(公告)日：2023-02-02

    申请号：US17967441

    申请日：2022-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

    IPC: H01L27/108 ,  G11C11/401

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

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