公开(公告)号：US06436773B1

公开(公告)日：2002-08-20

申请号：US09846842

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/4238 ,  H01L29/41758 ,  H01L29/6659

Abstract: For fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A dummy structure is formed on the gate electrode material, and the dummy structure is disposed over a shaped area of the gate electrode material and of the semiconductor substrate. The dummy structure has at least one sidewall around a perimeter of the shaped area. A spacer structure is formed to surround the at least one sidewall of the dummy structure outside of the perimeter of the shaped area. The dummy structure is etched away such that the shaped area of the gate electrode material is exposed and such that the spacer structure remains outside of the perimeter of the shaped area. Any exposed regions of the gate electrode material and of the gate dielectric material not under the spacer structure are etched away. The gate dielectric material remaining under the spacer structure forms a gate dielectric of the test field effect transistor, and the gate electrode material remaining under the spacer structure forms a gate electrode of the test field effect transistor. A drain and source dopant is implanted into exposed regions of the semiconductor substrate to form a first drain or source junction within the shaped area surrounded by the gate dielectric and the gate electrode, and to form a second drain or source junction outside the shaped area beyond the gate dielectric and the gate electrode. A width of the test field effect transistor is the perimeter of the shaped area, and a length of the test field effect transistor is the width of the gate dielectric and the gate electrode extending out from the perimeter of the shaped area.

Abstract translation: 为了在半导体衬底上制造测试场效应晶体管，在半导体衬底上沉积一层栅极电介质材料，并且在该栅极电介质材料层上沉积一层栅电极材料。 在栅电极材料上形成虚拟结构，并且将虚设结构设置在栅电极材料和半导体衬底的成形区域上。 虚拟结构具有围绕成形区域的周边的至少一个侧壁。 形成间隔结构以围绕该成形区域周边外部的该虚拟结构的至少一个侧壁。 蚀刻掉虚拟结构，使得栅电极材料的成形区域被暴露，并且使得间隔结构保持在成形区域的周边的外侧。 栅极电极材料的任何暴露区域和不在间隔结构下方的栅极电介质材料被蚀刻掉。 保留在间隔结构之下的栅极电介质材料形成测试场效应晶体管的栅极电介质，并且保留在间隔结构之下的栅电极材料形成测试场效应晶体管的栅电极。 将漏极和源极掺杂剂注入到半导体衬底的暴露区域中，以在由栅极电介质和栅极电极包围的成形区域内形成第一漏极或源极结，并且在成形区域外部形成超出第二漏极或源极结 栅极电介质和栅电极。 测试场效应晶体管的宽度是成形区域的周长，并且测试场效应晶体管的长度是从成形区域的周边延伸出的栅极电介质和栅电极的宽度。

公开(公告)号：US06429484B1

公开(公告)日：2002-08-06

申请号：US09633208

申请日：2000-08-07

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided above an insulative layer above the SOI substrate. Solid phase epitaxy can be used to form the second active layer. Subsequent active layers can be added by a similar technique. A seeding window can also be utilized.

Abstract translation: 集成电路包括多个有源层。 优选地，使用绝缘体上半导体（SOI）或绝缘体上硅晶片来容纳第一有源层。 第二有源层设置在SOI衬底上方的绝缘层的上方。 固相外延可用于形成第二活性层。 后续活动层可以通过类似的技术添加。 也可以使用播种窗。

公开(公告)号：US06414355B1

公开(公告)日：2002-07-02

申请号：US09770708

申请日：2001-01-26

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L2701

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.

Abstract translation: 绝缘体上硅（SOI）芯片。 SOI芯片具有基板; 设置在基板上的掩埋氧化物（BOX）层; 以及设置在所述BOX层上的有源层，所述有源层被分为第一和第二瓦片，所述第一瓦片具有第一厚度，所述第二瓦片具有第二厚度，所述第二厚度小于所述第一厚度。 还公开了一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。

公开(公告)号：US06406951B1

公开(公告)日：2002-06-18

申请号：US09781364

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21338

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/78618

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, an insulating block comprised of insulating material is formed on a thin semiconductor island comprised of semiconductor material. Semiconductor material is further grown from sidewalls of the semiconductor island to extend up along sidewalls of the insulating block to form a raised drain structure on a first side of the insulating block and the semiconductor island and to form a raised source structure on a second side of the insulating block and the semiconductor island. A drain and source dopant is implanted into the raised drain and source structures. A thermal anneal is performed to activate the drain and source dopant within the raised drain and source structures and such that the drain and source dopant extends partially into the semiconductor island. The insulating block is etched away to form a block opening, and a gate dielectric is deposited at a bottom wall of the block opening. The block opening is filled with a conductive material to form a gate structure disposed over the semiconductor island. The portion of the semiconductor island disposed under the gate structure forms a channel region that is fully depleted during operation of the field effect transistor. A drain silicide is formed within the raised drain structure, and a source silicide is formed within the raised source structure. In this manner, the drain and source silicides formed in the raised drain and source structures may be formed to have a higher thickness than the relatively thin semiconductor island to minimize series resistance at the drain and source of the field effect transistor.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在由半导体材料构成的薄半导体岛上形成由绝缘材料组成的绝缘块。 半导体材料进一步从半导体岛的侧壁生长，沿着绝缘块的侧壁向上延伸，以在绝缘块和半导体岛的第一侧上形成升高的漏极结构，并在第二侧上形成升高的源极结构 绝缘块和半导体岛。 漏极和源极掺杂剂被注入到升高的漏极和源极结构中。 执行热退火以激活凸起的漏极和源极结构内的漏极和源极掺杂剂，并且使得漏极和源极掺杂物部分地延伸到半导体岛中。 蚀刻绝缘块以形成块开口，并且栅极电介质沉积在块开口的底壁处。 块开口填充有导电材料以形成设置在半导体岛上的栅极结构。 设置在栅极结构下面的半导体岛的部分形成在场效应晶体管的工作期间完全耗尽的沟道区。 在升高的漏极结构内形成漏极硅化物，并且在升高的源极结构内形成源极硅化物。 以这种方式，在升高的漏极和源极结构中形成的漏极和源极硅化物可以形成为具有比相对薄的半导体岛更高的厚度，以最小化场效应晶体管的漏极和源极处的串联电阻。

公开(公告)号：US06403433B1

公开(公告)日：2002-06-11

申请号：US09397217

申请日：1999-09-16

Applicant: Bin Yu ,  Jonathan Kluth ,  Emi Ishida

Inventor： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。 在掺杂之前，升高的源极和漏极区非晶化。 中性离子物质可用于使提升的源极和漏极区域非晶化。 掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06383904B1

公开(公告)日：2002-05-07

申请号：US09690081

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6675 ,  H01L29/4908 ,  H01L29/78639 ,  H01L29/78648

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a first layer of dielectric material is formed on the semiconductor substrate, and a layer of amorphous semiconductor material is deposited on the first layer of dielectric material. A second layer of dielectric material is deposited on the layer of amorphous semiconductor material, and a front gate opening is etched through the second layer of dielectric material to expose the layer of amorphous semiconductor material through the front gate opening. An amorphization dopant is implanted into the semiconductor substrate through the front gate opening to form a back gate region of amorphous semiconductor material in the semiconductor substrate such that the back gate region is formed to be aligned under the front gate opening. In addition, a back gate dopant is implanted into the back gate region of amorphous semiconductor material through the front gate opening. A gate dielectric is formed at the bottom of the front gate opening to contact the layer of amorphous semiconductor material, and a remaining portion of the front gate opening is filled with a gate electrode material. In this manner, because the same front gate opening is used for forming both the front gate electrode and the back gate region, the front gate electrode and the back gate region are substantially aligned with each other to ensure that the back gate region overlaps the front gate electrode. Thus, the area of the back gate region is minimized to be substantially aligned to the area of the channel region under the gate dielectric. A minimized area of the back gate region in turn minimizes the parasitic capacitance from the back gate region to enhance the speed performance of the MOSFET.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在半导体衬底上形成第一层电介质材料，并且在第一绝缘材料层上沉积非晶半导体材料层。 第二层电介质材料沉积在非晶半导体材料层上，并且通过第二介电材料层蚀刻前栅极开口以通过前栅极开口暴露非晶半导体材料层。 非晶化掺杂剂通过前栅极开口注入到半导体衬底中，以在半导体衬底中形成非晶半导体材料的背栅极区域，使得背栅区域形成为在前栅极开口下对准。 此外，背栅掺杂剂通过前栅极开口注入到非晶半导体材料的背栅区域中。 栅极电介质形成在前栅极开口的底部以与非晶半导体材料层接触，并且前栅极开口的剩余部分填充有栅电极材料。 以这种方式，由于使用相同的前栅极开口来形成前栅极电极和后栅极区域，所以前栅电极和后栅极区域基本上彼此对准，以确保后栅极区域与前栅极区域重叠 栅电极。 因此，背栅极区域的面积被最小化以与栅极电介质下方的沟道区域的区域基本对齐。 背栅极区域的最小化面积进而将来自背栅极区域的寄生电容最小化，以增强MOSFET的速度性能。

公开(公告)号：US06356213B1

公开(公告)日：2002-03-12

申请号：US09583601

申请日：2000-05-31

Applicant: Dawei Huang ,  Bin Yu

Inventor： Dawei Huang ,  Bin Yu

IPC: H03M700

CPC classification number: G06T9/004 ,  H03M7/30

Abstract: A lossless encoding methodology is described based on residual coding techniques and using a modified Least Mean Squares methodology to develop a predictor for a signal to be encoded, and a residual as the difference between the signal and its predicted value. After the residual for an input signal segment is obtained according to the method of the invention, that method is again applied to the residual value process to develop a second predictor, from which a second residual value is obtained. The method is then applied for at least one further iteration to the most recently obtained residual value process to develop a third predictor for the signal to be encoded. A single prediction value is then selected as a statistical representative of those multiple predictor values. The residual value to be used for encoding the input signal increment is determined as the difference between the signal value and the selected predictor value.

Abstract translation: 基于残差编码技术描述无损编码方法，并使用经修改的最小均方法来修正要编码的信号的预测器，以及残差作为信号与其预测值之间的差值。 在根据本发明的方法获得输入信号段的残差之后，再次将该方法应用于剩余值过程以开发第二预测器，从其获得第二残差值。 然后将该方法应用于最近获得的残余值过程的至少一个进一步迭代，以开发待编码信号的第三预测器。 然后选择单个预测值作为那些多个预测值的统计代表。 将用于编码输入信号增量的剩余值确定为信号值和所选择的预测值之间的差值。

公开(公告)号：US06342410B1

公开(公告)日：2002-01-29

申请号：US09612781

申请日：2000-07-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor, a semiconductor pillar is formed on a layer of insulating material with a top surface and first and second side surfaces of the semiconductor pillar being exposed. A layer of dielectric material is formed on the top surface and the first and second side surfaces of the semiconductor pillar. A layer of conductive material is deposited on the layer of dielectric material on the top surface and the first and second side surfaces of the semiconductor pillar. A dummy dielectric structure is formed that covers a portion of the layer of conductive material such that a remaining portion of the layer of conductive material on the semiconductor pillar is exposed. The dummy dielectric structure has a predetermined sidewall on the layer of conductive material on the semiconductor pillar. A layer of hardmask dielectric is deposited on top and on the predetermined sidewall of the dummy dielectric structure and on the remaining portion of the layer of conductive material that is exposed. The layer of hardmask dielectric is anisotropically etched such that the hardmask dielectric remains at the predetermined sidewall of the dummy dielectric structure to form a spacer of hardmask dielectric. Any exposed region of the layer of conductive material and the layer of dielectric material not covered by the spacer of hardmask dielectric is etched away. The conductive material and the dielectric material that remain on the top surface and the first and second side surfaces at the gate portion of the semiconductor pillar form a three-sided gate structure and a three-sided gate dielectric of the field effect transistor for minimizing short channel effects in the field effect transistor.

Abstract translation: 为了制造场效应晶体管，半导体柱形成在绝缘材料层上，半导体柱的上表面和第一和第二侧表面露出。 在半导体柱的顶表面和第一和第二侧表面上形成介电材料层。 一层导电材料沉积在半导体柱的顶表面和第一和第二侧表面上的电介质材料层上。 形成覆盖导电材料层的一部分的虚拟介电结构，使得半导体柱上的导电材料层的剩余部分露出。 虚设电介质结构在半导体柱上的导电材料层上具有预定的侧壁。 一层硬掩模电介质沉积在虚拟电介质结构的顶部和预定侧壁上以及暴露的导电材料层的剩余部分上。 硬掩模电介质层被各向异性地蚀刻，使得硬掩模电介质保留在虚拟电介质结构的预定侧壁处以形成硬掩模电介质的间隔物。 导电材料层的任何暴露区域和未被硬掩模电介质间隔物覆盖的电介质材料层被蚀刻掉。 保留在顶表面上的导电材料和电介质材料以及在半导体柱的栅极部分处的第一和第二侧表面形成用于最小化短路的场效应晶体管的三面栅极结构和三面栅极电介质 通道效应在场效应晶体管中。

公开(公告)号：US06333244B1

公开(公告)日：2001-12-25

申请号：US09491422

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2972

CPC classification number: H01L21/8238

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). In the case of a P-channel MOSFET, a nitrogen barrier is formed in the P-channel gate prior to p+ doping. Annealing the gate conductor is done in a step separate from the source/drain region annealing step.

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。 该技术产生浅的非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的150-200nm之间。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。 在P沟道MOSFET的情况下，在P +掺杂之前，在P沟道栅极中形成氮势垒。 在与源极/漏极区域退火步骤分离的步骤中进行栅极导体的退火。

公开(公告)号：US06320228B1

公开(公告)日：2001-11-20

申请号：US09483678

申请日：2000-01-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L27/1203

Abstract: An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided by bonding a bulk substrate to the SOI substrate and removing the bulk substrate to leave a thin semiconductor layer. Subsequent active layers can be added by a similar technique. Preferably, the bulk substrates utilize a hydrogen implant to provide a breaking interface.

Abstract translation: 集成电路包括多个有源层。 优选地，使用绝缘体上半导体（SOI）或绝缘体上硅晶片来容纳第一有源层。 通过将体基板结合到SOI衬底并去除体基板以留下薄的半导体层来提供第二有源层。 后续活动层可以通过类似的技术添加。 优选地，本体衬底利用氢注入来提供断开界面。