公开(公告)号：US06451693B1

公开(公告)日：2002-09-17

申请号：US09679370

申请日：2000-10-05

Applicant: Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

Inventor： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC: H01L2144

CPC classification number: H01L29/66613 ,  H01L21/28518 ,  H01L29/66507

Abstract: A silicide gate contact is formed which is relatively thicker than silicide contacts formed over source/drain regions and shallow junction extensions. A metal layer is first deposited to form silicide over the polysilicon gate and the source/drain extension regions. The silicide is removed from the extension regions, forming shallow junctions, and a layer of silicide remains on the polysilicon gate. A second metal deposition step and silicidation step forms silicide contacts over the source/drain regions and the polysilicon gate. The resulting silicide gate contact is thicker than the resulting silicide contacts over the source/drain regions.

Abstract translation: 形成硅化物栅极接触，其比在源极/漏极区域和浅结延伸部分上形成的硅化物触点相对更厚。 首先沉积金属层以在多晶硅栅极和源极/漏极延伸区域上形成硅化物。 从延伸区域去除硅化物，形成浅结，并且多晶硅栅极上保留一层硅化物。 第二金属沉积步骤和硅化步骤在源极/漏极区域和多晶硅栅极之上形成硅化物接触。 所得到的硅化物栅极接触比源极/漏极区上的所得硅化物接触厚。

公开(公告)号：US06403433B1

公开(公告)日：2002-06-11

申请号：US09397217

申请日：1999-09-16

Applicant: Bin Yu ,  Jonathan Kluth ,  Emi Ishida

Inventor： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。 在掺杂之前，升高的源极和漏极区非晶化。 中性离子物质可用于使提升的源极和漏极区域非晶化。 掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06387767B1

公开(公告)日：2002-05-14

申请号：US09781448

申请日：2001-02-13

Applicant: Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

Inventor： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC: H01L21336

CPC classification number: H01L29/665

Abstract: Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

Abstract translation: 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06362095B1

公开(公告)日：2002-03-26

申请号：US09679876

申请日：2000-10-05

Applicant: Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Jacques Bertrand

Inventor： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Jacques Bertrand

IPC: H01L214763

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

Abstract translation: 一种制造MOSFET半导体器件的方法包括在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 在栅电极和衬底之间提供栅极氧化物; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 形成设置在源极/漏极区域和栅电极上的硅化镍层，以及两个蚀刻步骤。 在约380-600℃的温度下，在快速热退火期间形成硅化镍层。用硫酸过氧化物混合物进行第一次蚀刻以除去未反应的镍，并且用氨过氧化物混合物进行第二次蚀刻以除去镍 硅化物形成在第一和第二侧壁间隔物上。

公开(公告)号：US06521501B1

公开(公告)日：2003-02-18

申请号：US09310170

申请日：1999-05-11

Applicant: Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

Inventor： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract translation: 一种形成CMOS结构的方法，所述方法包括以下动作：在衬底层上形成栅极结构; 在衬底层上形成硅化物层; 在衬底层中形成浅的源极/漏极区域; 在所述结构上形成氧化物扩散阻挡层; 在所述氧化物扩散阻挡层上形成金属吸收层; 并且将衬底层的部分直接覆盖在浅源极/漏极区域上，从而将浅的源极/漏极区域变换成浅的源极/漏极区域。 熔化的行为包括将金属吸收层暴露于脉冲激光束的行为。

公开(公告)号：US06878559B2

公开(公告)日：2005-04-12

申请号：US10253121

申请日：2002-09-23

Applicant: Peter G. Borden ,  G. Jonathan Kluth ,  Eric Paton

Inventor： Peter G. Borden ,  G. Jonathan Kluth ,  Eric Paton

IPC: G01N21/21 ,  G01N21/84 ,  G01N21/95 ,  G01N21/956 ,  G01R31/311 ,  H01L23/544 ,  H01L21/66

CPC classification number: H01L22/34 ,  G01N21/21 ,  G01N21/9501 ,  G01N21/95607 ,  G01N2021/8416 ,  G01N2201/0691 ,  G01R31/311 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.

公开(公告)号：US06562717B1

公开(公告)日：2003-05-13

申请号：US09679874

申请日：2000-10-05

Applicant: Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

Inventor： Christy Mei-Chu Woo ,  George Jonathan Kluth ,  Qi Xiang

IPC: H01L2144

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; and forming first and second nickel silicide layer respectively disposed on the source/drain regions and the gate electrode. The nickel silicide layer over the gate electrode can be thicker than the nickel silicide layer over the source/drain regions. A semiconductor device formed from the method is also disclosed.

Abstract translation: 一种制造半导体器件的方法包括：在具有源极/漏极区域的衬底上提供具有第一和第二相对侧壁的栅电极; 形成分别设置在所述第一和第二侧壁附近的第一和第二侧壁间隔件; 以及形成分别设置在源极/漏极区域和栅极电极上的第一和第二硅化镍层。 栅电极上的硅化镍层可以比源/漏区上的硅化镍层厚。 还公开了由该方法形成的半导体器件。

公开(公告)号：US06521515B1

公开(公告)日：2003-02-18

申请号：US09662820

申请日：2000-09-15

Applicant: George Jonathan Kluth

Inventor： George Jonathan Kluth

IPC: H01L2120

CPC classification number: H01L21/28518

Abstract: Metal silicides form low resistance contacts on semiconductor devices such as transistors. Rough interfaces are formed between metal silicide contacts, such as NiSi and the source/drain regions of a transistor, such as doped source/drain regions. Interfaces with a high degree of roughness result in increased spiking and junction leakage. Interface roughness is minimized by deeply doping the source/drain regions of a silicon on insulator substrate.

Abstract translation: 金属硅化物在诸如晶体管的半导体器件上形成低电阻接触。 在诸如NiSi的金属硅化物触点和诸如掺杂源极/漏极区域的晶体管的源极/漏极区域之间形成粗糙界面。 高度粗糙度的接口会增加尖峰和结漏。 通过深度掺杂绝缘体上硅衬底的源/漏区来最小化界面粗糙度。

公开(公告)号：US06380057B1

公开(公告)日：2002-04-30

申请号：US09781225

申请日：2001-02-13

Applicant: Matthew S. Buynoski ,  George Jonathan Kluth ,  Paul R. Besser ,  Paul L. King

Inventor： Matthew S. Buynoski ,  George Jonathan Kluth ,  Paul R. Besser ,  Paul L. King

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518

Abstract: Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.

Abstract translation: 镍自杀化处理通过在沉积Ni之前将镍注入活性区域来实现，以在退火期间催化Ni和Si的反应，以在多晶硅栅极电极和源极/漏极区域上形成NiSi层，而不形成在 硅化镍层和底层硅，并且在栅电极上的金属硅化物层与相关源极/漏极区域上的金属硅化物层之间没有导电桥接，特别是在存在氮化硅侧壁间隔物的情况下。

公开(公告)号：US06372673B1

公开(公告)日：2002-04-16

申请号：US09781256

申请日：2001-02-13

Applicant: Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

Inventor： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC: H01L21318

CPC classification number: H01L29/665 ,  H01L21/3185

Abstract: Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

Abstract translation: 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。