公开(公告)号：US06356213B1

公开(公告)日：2002-03-12

申请号：US09583601

申请日：2000-05-31

Applicant: Dawei Huang ,  Bin Yu

Inventor： Dawei Huang ,  Bin Yu

IPC: H03M700

CPC classification number: G06T9/004 ,  H03M7/30

Abstract: A lossless encoding methodology is described based on residual coding techniques and using a modified Least Mean Squares methodology to develop a predictor for a signal to be encoded, and a residual as the difference between the signal and its predicted value. After the residual for an input signal segment is obtained according to the method of the invention, that method is again applied to the residual value process to develop a second predictor, from which a second residual value is obtained. The method is then applied for at least one further iteration to the most recently obtained residual value process to develop a third predictor for the signal to be encoded. A single prediction value is then selected as a statistical representative of those multiple predictor values. The residual value to be used for encoding the input signal increment is determined as the difference between the signal value and the selected predictor value.

Abstract translation: 基于残差编码技术描述无损编码方法，并使用经修改的最小均方法来修正要编码的信号的预测器，以及残差作为信号与其预测值之间的差值。 在根据本发明的方法获得输入信号段的残差之后，再次将该方法应用于剩余值过程以开发第二预测器，从其获得第二残差值。 然后将该方法应用于最近获得的残余值过程的至少一个进一步迭代，以开发待编码信号的第三预测器。 然后选择单个预测值作为那些多个预测值的统计代表。 将用于编码输入信号增量的剩余值确定为信号值和所选择的预测值之间的差值。

公开(公告)号：US08009763B2

公开(公告)日：2011-08-30

申请号：US12061217

申请日：2008-04-02

Applicant: Gabriel Risk ,  Dawei Huang ,  Drew Doblar

Inventor： Gabriel Risk ,  Dawei Huang ,  Drew Doblar

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC classification number: H04L25/0288 ,  H04L25/03343

Abstract: A method and apparatus for equalizing a reflection in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a compensating pulse that is transmitted in response to a pulse transmitted on the serial link. The apparatus comprises a programmable delay element and a driver stage configured to transmit a delayed and amplitude adjusted version of a pulse transmitted on the serial link. A method for equalizing a plurality of reflections in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a first compensating pulse and an amplitude and delay time of a second compensating pulse. The method further involves transmitting the first compensating and second compensating pulses in response to a pulse transmitted on the serial link.

Abstract translation: 一种用于均衡反射高速串行链路中的反射的方法和装置。 该方法包括获得响应于在串行链路上发送的脉冲而发送的补偿脉冲的幅度和延迟时间。 该装置包括可编程延迟元件和驱动器级，其被配置为传送在串行链路上传输的脉冲的延迟和幅度调整版本。 一种用于均衡反射高速串行链路中的多个反射的方法。 该方法包括获得第一补偿脉冲的幅度和延迟时间以及第二补偿脉冲的幅度和延迟时间。 该方法还包括响应于在串行链路上发送的脉冲发送第一补偿和第二补偿脉冲。

公开(公告)号：US20100158182A1

公开(公告)日：2010-06-24

申请号：US12343426

申请日：2008-12-23

Applicant: Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

Inventor： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

IPC: H03D3/24

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04L25/061

Abstract: A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

Abstract translation: 提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。 数据信号通过第一通道发送到接收器。 时钟信号通过第二通道发送到接收器。 在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

公开(公告)号：US20100158177A1

公开(公告)日：2010-06-24

申请号：US12342825

申请日：2008-12-23

Applicant: Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

Inventor： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

IPC: H04L7/00

CPC classification number: H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

Abstract: A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

Abstract translation: 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

公开(公告)号：US20070097264A1

公开(公告)日：2007-05-03

申请号：US11265885

申请日：2005-11-02

Applicant: Gabriel Risk ,  Dawei Huang ,  Jason Bau

Inventor： Gabriel Risk ,  Dawei Huang ,  Jason Bau

IPC: H04N7/00

CPC classification number: H04L7/0083 ,  H04L7/046 ,  H04L7/10 ,  H04L2007/045

Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.

Abstract translation: 改进的时钟和数据恢复涉及在发送同步帧之前发送一个或多个空帧。 接收组件检测同步帧锁定到由发射组件在信号路径上发送的数据信号。 在同步帧之前发送的一个或多个空帧在接收到同步帧之前导致信号路径的建立，从而减少或消除先前在同步帧上发送的数据的影响。

公开(公告)号：US07170946B2

公开(公告)日：2007-01-30

申请号：US10090237

申请日：2002-03-04

Applicant: Dawei Huang

Inventor： Dawei Huang

IPC: H04L23/02

CPC classification number: H04L1/006 ,  H03M13/23 ,  H03M13/47 ,  H04L1/0054

Abstract: A system and method of the present invention revives a catastrophic code used for channel coding data. A data receiving circuit receives a digital input data sequence to be coded with a code having a distance spectrum containing an infinite component that corresponds to a finite hamming weight such that the code may cause catastrophic error propagation. The circuit is operative for periodically inserting known symbols into the digital input data sequence. An encoder, such as a convolutional encoder, is operatively connected to the data receiving circuit and encodes the digital input data sequence.

Abstract translation: 本发明的系统和方法恢复用于信道编码数据的灾难性代码。 数据接收电路接收要用具有包含对应于有限汉明权重的无限分量的距离谱的代码进行编码的数字输入数据序列，使得代码可能导致灾难性错误传播。 该电路用于将已知符号周期性地插入到数字输入数据序列中。 诸如卷积编码器的编码器可操作地连接到数据接收电路并对数字输入数据序列进行编码。

公开(公告)号：US20060067538A1

公开(公告)日：2006-03-30

申请号：US11068578

申请日：2005-02-28

Applicant: Dawei Huang

Inventor： Dawei Huang

IPC: A61F11/06

CPC classification number: G10K11/178 ,  G10K2210/1081 ,  G10K2210/3224

Abstract: An acoustic device includes a resonance chamber and a noise reduction unit. The noise reduction unit serves to combat noise in the resonance chamber, and includes first and second electro-acoustic transducers, a controller, and a sound-absorbing member. The first electro-acoustic transducer generates a first electrical signal that corresponds to the noise in the resonance chamber. The controller generates a second electrical signal. The second electro-acoustic transducer generates a sound wave that corresponds to the second electrical signal and that counteracts a portion of the noise in the resonance chamber. The sound-absorbing member includes a porous body that is mounted in that resonance chamber and that absorbs another portion of the noise in the resonance chamber.

Abstract translation: 声学装置包括共振室和降噪单元。 噪声降低单元用于抵消共振室中的噪声，并且包括第一和第二电声换能器，控制器和吸音构件。 第一电声换能器产生对应于谐振室中的噪声的第一电信号。 控制器产生第二电信号。 第二电声换能器产生对应于第二电信号并且抵消共振室中的噪声的一部分的声波。 吸声构件包括安装在该共振室中并且吸收共振室中的噪声的另一部分的多孔体。

公开(公告)号：US06619858B1

公开(公告)日：2003-09-16

申请号：US09575418

申请日：2000-05-20

Applicant: Rick Lytel ,  Howard Davidson ,  Theresa Sze ,  Nyles Nettleton ,  Dawei Huang

Inventor： Rick Lytel ,  Howard Davidson ,  Theresa Sze ,  Nyles Nettleton ,  Dawei Huang

IPC: G02B636

CPC classification number: G02B6/43 ,  G02B6/4249

Abstract: An optical interconnect is provided that optically connects two adjacent printed circuit boards, or electrical component. The optical interconnect includes a floating frame which is flexibly connected to one electrical component. The floating frame includes a plurality of optical guides. The optical guides are connected to the electrical component either electronically or optically. A second frame, coupled to a second electrical component also contains a plurality of optical guides. A mechanical guide assembly positions the first frame and the second frame are optically coupled. The optical guide in the second frame connects to the second electrical component providing a path for a signal from the first electrical component to the second electrical component.

Abstract translation: 提供光学互连以光学连接两个相邻的印刷电路板或电气部件。 光学互连包括浮动框架，该浮动框架柔性地连接到一个电气部件。 浮动框架包括多个光导件。 光导件以电子方式或光学方式连接到电气部件。 耦合到第二电气部件的第二框架还包含多个光导件。 机械引导组件定位第一框架并且第二框架被光耦合。 第二框架中的光导件连接到第二电气部件，从而提供用于从第一电气部件到第二电气部件的信号的路径。

公开(公告)号：US20120033685A1

公开(公告)日：2012-02-09

申请号：US12850535

申请日：2010-08-04

Applicant: Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

Inventor： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

IPC: H04J3/04 ,  G01R19/00

CPC classification number: H04L25/03057 ,  H04L25/061 ,  H04L25/14

Abstract: This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Abstract translation: 本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。 这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。 换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。 因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

公开(公告)号：US20110261900A1

公开(公告)日：2011-10-27

申请号：US13175589

申请日：2011-07-01

Applicant: Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

Inventor： Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

IPC: H04L27/00

CPC classification number: H04L25/068

Abstract: A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

Abstract translation: 提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。 在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。 接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。 通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。