公开(公告)号：US11749746B2

公开(公告)日：2023-09-05

申请号：US17244293

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01L29/737 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/08 ,  H01L24/80 ,  H01L29/205 ,  H01L29/66318 ,  H01L2224/08165 ,  H01L2224/80001

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

公开(公告)号：US11670614B2

公开(公告)日：2023-06-06

申请号：US17061737

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram ,  Abdolreza Langari

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/29 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/27 ,  H01L2924/01014 ,  H01L2924/1205 ,  H01L2924/14

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

公开(公告)号：US11658103B2

公开(公告)日：2023-05-23

申请号：US17323249

申请日：2021-05-18

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Jinseong Kim

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/64

CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/642

Abstract: An integrated circuit (IC) package includes a chip. The chip has a front-side surface and a backside surface, opposite the front-side surface. The front-side surface of the chip includes a plurality of bump sites. The integrated circuit package also includes a plurality of dies. Each of the plurality of dies are composed of integrated passive devices. The plurality of dies have conformal die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.

公开(公告)号：US11631614B2

公开(公告)日：2023-04-18

申请号：US17536464

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Jin-Su Ko ,  Beomsup Kim ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.

公开(公告)号：US11626236B2

公开(公告)日：2023-04-11

申请号：US17195220

申请日：2021-03-08

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H03H7/01 ,  H04B1/18 ,  H04B1/40

Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

公开(公告)号：US20230088569A1

公开(公告)日：2023-03-23

申请号：US17482733

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01L27/12 ,  H01L23/66 ,  H01L21/762 ,  H01L21/84

Abstract: Radio frequency (RF) circuits generate noise that can interfere with other RF circuits on the same semiconductor die. An isolation material disposed in an isolation region between a first active region of a first RF circuit and a second active region of a second RF circuit comprises a porosified region of the semiconductor material of the semiconductor die. The isolation material (e.g., porosified material) has a higher resistivity and lower permittivity than the semiconductor material to reduce transmission of noise interference between the first RF circuit and the second RF circuit. The isolation material in the isolation region of the semiconductor material comprises a porosity in the range 20% to 50% higher than the porosity of the semiconductor material in the first and second active regions. The porosified region has a lower permittivity and a higher resistivity than the non-porosified region to protect against the transmission of noise interference.

公开(公告)号：US11605620B2

公开(公告)日：2023-03-14

申请号：US16906509

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Ranadeep Dutta ,  Jonghae Kim

IPC: H01L25/16 ,  H01L23/00 ,  H01L49/02 ,  H01L27/092 ,  H03H9/17

Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

公开(公告)号：US20230054636A1

公开(公告)日：2023-02-23

申请号：US17409282

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H03H9/64 ,  H03H3/10 ,  H03H9/10 ,  H03H9/05 ,  H03H9/02

Abstract: Surface acoustic wave (SAW) filter packages employing an enhanced thermally conductive cavity frame for heat dissipation, and related fabrication methods are disclosed. The SAW filter package also includes a cavity frame comprising a perimeter structure and a cavity inside the perimeter structure coupled to a substrate of a piezoelectric material that contains interdigital transducers (IDTs). A cap substrate is disposed on the perimeter structure of the cavity frame to enclose an air cavity inside the perimeter structure between a substrate and the cap substrate. In exemplary aspects, to effectively dissipate heat generated in the SAW filter package to maintain the desired performance of the SAW filter, the cavity frame is comprised of a material that has an enhanced thermal conductivity. The heat generated in the SAW filter package can more effectively be dissipated, particularly at edges and corners of the cavity frame where hot spots can particularly occur.

公开(公告)号：US11417637B2

公开(公告)日：2022-08-16

申请号：US16864363

申请日：2020-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H05K1/18 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00 ,  H01L49/02 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

公开(公告)号：US11342246B2

公开(公告)日：2022-05-24

申请号：US16934559

申请日：2020-07-21

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Jonghae Kim ,  Hong Bok We

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: An integrated circuit (IC) package is described. The IC package includes a die. The die including an active layer on a substrate and through substrate vias (TSVs) coupled to the active layer and extending through the substrate to a backside surface of the die. The IC package also includes integrated passive devices (IPDs) on the backside surface of the die and coupled to the active layer through the TSVs. The IC package further includes back-end-of-line (BEOL) layers on the active layer. The IC package also includes a metallization structure on the BEOL layers. The IC package also includes an under bump metallization layer on the metallization structure. The IC package further includes package bumps on the first under bump metallization layer.