公开(公告)号：US10855222B2

公开(公告)日：2020-12-01

申请号：US16023698

申请日：2018-06-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Dirk J. Robinson ,  Andy Huei Chu ,  Yan Sun ,  Saket Sham Doshi

IPC: H03B5/06 ,  G05F1/10 ,  H03B5/04 ,  H03K5/00

Abstract: A clock synthesizer has integrated voltage droop detection and clock stretching. An oscillator of the clock synthesizer receives a control current from a digital to analog converter and generates an oscillator output signal. A droop detector and clock stretching circuit responds to a voltage droop of a supply voltage supplying circuits coupled to the oscillator output signal, to cause a portion of the oscillator control current to be diverted from the oscillator to thereby cause the oscillator to reduce the first frequency. The diversion can be accomplished through shunt circuits or a current mirror circuit.

公开(公告)号：US20200296393A1

公开(公告)日：2020-09-17

申请号：US16818999

申请日：2020-03-13

Applicant: ATI Technologies ULC

Inventor： Mehdi Saeedi ,  Boris Ivanovic

IPC: H04N19/196 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: Techniques are provided herein for processing video data. The techniques include generating predicted macroblock coding modes for a set of macroblocks of a frame, assigning quantization parameters to the macroblocks based on the predicted macroblock coding modes, and encoding the set of macroblocks based on the quantization parameters.

公开(公告)号：US10771818B2

公开(公告)日：2020-09-08

申请号：US16409415

申请日：2019-05-10

Applicant: ATI TECHNOLOGIES ULC

Inventor： Ihab Amer ,  Gabor Sines ,  Khaled Mammou ,  Haibo Liu ,  Edward Harold ,  Lei Zhang ,  Fabio Gulino ,  Ehsan Mirhadi ,  Ho Hin Lau

IPC: H04N19/65 ,  H04N21/44 ,  H04N19/44 ,  H04N21/442 ,  H04N21/6375

Abstract: An encoder encodes pixels representative of a picture in a multimedia stream, generates a first approximate signature based on approximate values of pixels in a reconstructed copy of the picture, and transmits the encoded pixels and the first approximate signature. A decoder receives a first packet including the encoded pixels and the first approximate signature, decodes the encoded pixels, and transmits a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels. If a corrupted packet is detected, the multimedia application requests an intra-coded picture in response to the first approximate signature differing from the second approximate signature. The second signal instructs the decoder to bypass requesting an intra-coded picture and to continue decoding received packets in response to the first approximate signature being equal to the second approximate signature.

公开(公告)号：US10699361B2

公开(公告)日：2020-06-30

申请号：US13683546

申请日：2012-11-21

Applicant: ATI Technologies ULC

Inventor： Khaled Mammou

IPC: G06T15/00 ,  G06T1/20 ,  G06T9/00

Abstract: A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space.

公开(公告)号：US10698856B1

公开(公告)日：2020-06-30

申请号：US16223873

申请日：2018-12-18

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/376 ,  G06F13/38 ,  G06F13/16 ,  G06F13/22

Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

公开(公告)号：US10678733B2

公开(公告)日：2020-06-09

申请号：US16380005

申请日：2019-04-10

Applicant: ATI Technologies ULC

Inventor： Nima Osqueizadeh

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/16

Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

公开(公告)号：US20200169760A1

公开(公告)日：2020-05-28

申请号：US16203326

申请日：2018-11-28

Applicant: ATI Technologies ULC

Inventor： Jiao Wang ,  Lei Zhang ,  Ying Zhang ,  Edward A. Harold

IPC: H04N19/87 ,  H04N19/142 ,  H04N19/132 ,  H04N19/159 ,  H04N19/179 ,  H04N19/176

Abstract: Systems, methods, and devices for scene change detection and image encoding. A sequence of image frames is input. For a first image frame of the sequence, a first total sum of absolute transformed differences (SATD) is calculated. For a second frame of the sequence, a second total SATD is calculated. An absolute difference between the first total SATD and the second total SATD is calculated. If the absolute difference meets or exceeds a threshold, the second frame and a third frame of the sequence subsequent to the second frame are encoded based on a scene change, and the second frame and the third frame are transmitted. If the absolute difference does not meet or exceed the threshold, the second frame is encoded based on a same scene and the second frame is transmitted.

公开(公告)号：US10659796B2

公开(公告)日：2020-05-19

申请号：US16126704

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Ji Zhou ,  Zhen Chen ,  Min Yu

IPC: H04N19/159 ,  H04N19/33 ,  H04N19/423 ,  H04N19/117 ,  H04N19/187 ,  H04N19/80 ,  H04N19/59

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

公开(公告)号：US10580110B2

公开(公告)日：2020-03-03

申请号：US15496637

申请日：2017-04-25

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Al Hasanur Rahman ,  Sergey Korobkov ,  Houman Namiranian

IPC: G06T1/60 ,  G06F13/24 ,  G06F12/1009 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

公开(公告)号：US10535178B2

公开(公告)日：2020-01-14

申请号：US15389075

申请日：2016-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jimshed Mirza ,  Christopher J. Brennan ,  Anthony Chan ,  Leon Lai

IPC: G06T15/50 ,  G06T15/00 ,  G06F12/0875 ,  G06T15/04 ,  G06T15/80

Abstract: Systems, apparatuses, and methods for performing shader writes to compressed surfaces are disclosed. In one embodiment, a processor includes at least a memory and one or more shader units. In one embodiment, a shader unit of the processor is configured to receive a write request targeted to a compressed surface. The shader unit is configured to identify a first block of the compressed surface targeted by the write request. Responsive to determining the data of the write request targets less than the entirety of the first block, the first shader unit reads the first block from the cache and decompress the first block. Next, the first shader unit merges the data of the write request with the decompressed first block. Then, the shader unit compresses the merged data and writes the merged data to the cache.