公开(公告)号：US20230092413A1

公开(公告)日：2023-03-23

申请号：US17800299

申请日：2021-02-15

Applicant: STMicroelectronics International N.V.

Inventor： Renaud Lemoine ,  Samia Ouyahia ,  Eric Wilhelm ,  Christophe Boyavalle

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/195 ,  H04B1/04

Abstract: According to one aspect, an integrated circuit having a radio frequency amplifier includes at least two amplifier stages and an impedance matching device between two amplifier stages of the radio frequency amplifier. The matching device includes two lines which are coupled by electromagnetic induction. The first line is connected to an output of the first amplifier stage and the second line is connected to an input of the second amplifier stage.

公开(公告)号：US11611275B2

公开(公告)日：2023-03-21

申请号：US17866372

申请日：2022-07-15

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07 ,  G11C5/14

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US20230082905A1

公开(公告)日：2023-03-16

申请号：US17800290

申请日：2021-02-15

Applicant: STMicroelectronics International N.V.

Inventor： Herve Guegnaud ,  Stephanie Venec ,  Guillaume Blamon

IPC: H03F1/52 ,  H03F3/24

Abstract: According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.

公开(公告)号：US20230061509A1

公开(公告)日：2023-03-02

申请号：US17876263

申请日：2022-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Sharad GUPTA ,  Ankur BAL

IPC: H03M1/06

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

公开(公告)号：US11593609B2

公开(公告)日：2023-02-28

申请号：US16794062

申请日：2020-02-18

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe Desoli ,  Carmine Cappetta ,  Thomas Boesch ,  Surinder Pal Singh ,  Saumya Suneja

IPC: G06N3/04 ,  G06F16/22 ,  G06K9/62 ,  G06N3/063 ,  G06N3/08

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US20230047409A1

公开(公告)日：2023-02-16

申请号：US17401702

申请日：2021-08-13

Applicant: STMicroelectronics International N.V.

Inventor： Kamaldeep Bansal ,  Alok Kumar Mittal ,  Jitendra Jain

IPC: H04L12/24 ,  H04W4/80

Abstract: A method to provision a node network including provisioning a first generation of nodes by a root node; and provisioning a second generation of nodes by the first generation of nodes. Wherein at least one node from the first generation of nodes or the second generation of nodes is provisioned simultaneously with at least one other node from the first generation of nodes or the second generation of nodes.

公开(公告)号：US20230042541A1

公开(公告)日：2023-02-09

申请号：US17443556

申请日：2021-07-27

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/22 ,  G11C7/10 ,  G11C29/36 ,  G11C29/14

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.

公开(公告)号：US20230024278A1

公开(公告)日：2023-01-26

申请号：US17860959

申请日：2022-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta

IPC: G01R31/40

Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.

公开(公告)号：US20230022608A1

公开(公告)日：2023-01-26

申请号：US17383547

申请日：2021-07-23

Applicant: STMicroelectronics International N.V.

Inventor： Subodh Vikram SHUKLA ,  Saurabh SONA

IPC: B60R25/04 ,  G06F21/44 ,  G06F21/60 ,  H02P27/06 ,  H04B10/80

Abstract: Described herein is an electric motor drive system, including at least one power phase line, an external controller configured to generate a drive signal and provide the drive signal to the at least one power phase line, and motor electronics. The motor electronics include at least one switch coupled between the at least one power phase line and at least one electric motor terminal, and an internal controller configured to cooperate with the external controller to perform an authentication process therebetween. The external controller is further configured to cause the at least one switch to electrically couple the at least one power phase line to the at least one electric motor terminal in response to success of the authentication process.

公开(公告)号：US11563436B2

公开(公告)日：2023-01-24

申请号：US17863708

申请日：2022-07-13

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee ,  Anand Kumar ,  Ankit Gupta

IPC: H03L7/089 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.