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    Programmable-on-the-fly fractional divider in accordance with this disclosure
    1.
    发明授权
    Programmable-on-the-fly fractional divider in accordance with this disclosure 有权

    公开(公告)号：US11251784B2

    公开(公告)日：2022-02-15

    申请号：US17193532

    申请日：2021-03-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Jeet Narayan Tiwari ,  Anand Kumar ,  Prashutosh Gupta

    IPC: H03K5/00 ,  H03K19/20 ,  H03L7/197

    Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

    Adaptive low power common mode buffer
    2.
    发明授权
    Adaptive low power common mode buffer 有权

    公开(公告)号：US11025263B2

    公开(公告)日：2021-06-01

    申请号：US16896950

    申请日：2020-06-09

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Ramji Gupta

    IPC: H03M1/12

    Abstract: An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

    SPREAD SPECTRUM CLOCK GENERATOR
    3.
    发明申请
    SPREAD SPECTRUM CLOCK GENERATOR 有权

    公开(公告)号：US20180062661A1

    公开(公告)日：2018-03-01

    申请号：US15251065

    申请日：2016-08-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Gagan Midha

    IPC: H03L7/093 ,  H03L7/099 ,  H03L7/089 ,  H03L7/197

    CPC classification number: H03L7/093 ,  H03C3/095 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/1976 ,  H04B1/69

    Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

    Clock glitch and loss detection circuit
    4.
    发明授权
    Clock glitch and loss detection circuit 有权
    时钟毛刺和损耗检测电路

    公开(公告)号：US09413346B2

    公开(公告)日：2016-08-09

    申请号：US14219142

    申请日：2014-03-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar

    IPC: H03K5/19 ,  H03K5/22

    CPC classification number: H03K5/22

    Abstract: A conversion circuit measures individual period lengths for periods of a clock signal. Two of the measured period lengths are selected and compared. The comparison operates to compare a first period length against a threshold set as a function of the second period length. The result of the comparison is indicative of the presence of a clock error. If the threshold is set less than the second period length, the comparison functions to detect a clock glitch. If the threshold is set more than the second period, the comparison functions to detect a loss of clock. The result of the comparison may be used to control further handling of the clock signal by, for example, blocking logic state changes in the clock signal for the length of one period in response to the detection of the clock error.

    Abstract translation: A转换电路测量时钟信号周期中的各个周期长度。 选择和比较两个测量周期长度。 比较操作以将第一周期长度与作为第二周期长度的函数设置的阈值进行比较。 比较结果表明存在时钟误差。 如果阈值设置为小于第二周期长度，则比较功能用于检测时钟毛刺。 如果阈值设置大于第二个周期，则比较功能用于检测时钟损耗。 比较的结果可以用于通过例如响应于时钟误差的检测在一个周期的长度上阻塞时钟信号中的逻辑状态变化来控制时钟信号的进一步处理。

    CLOCK GLITCH AND LOSS DETECTION CIRCUIT
    5.
    发明申请
    CLOCK GLITCH AND LOSS DETECTION CIRCUIT 有权
    CLOCK GLITCH和LOSS DETECTION CIRCUIT

    公开(公告)号：US20150270836A1

    公开(公告)日：2015-09-24

    申请号：US14219142

    申请日：2014-03-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar

    IPC: H03K5/22

    CPC classification number: H03K5/22

    Abstract: A conversion circuit measures individual period lengths for periods of a clock signal. Two of the measured period lengths are selected and compared. The comparison operates to compare a first period length against a threshold set as a function of the second period length. The result of the comparison is indicative of the presence of a clock error. If the threshold is set less than the second period length, the comparison functions to detect a clock glitch. If the threshold is set more than the second period, the comparison functions to detect a loss of clock. The result of the comparison may be used to control further handling of the clock signal by, for example, blocking logic state changes in the clock signal for the length of one period in response to the detection of the clock error.

    Abstract translation: A转换电路测量时钟信号周期中的各个周期长度。 选择和比较两个测量周期长度。 比较操作以将第一周期长度与作为第二周期长度的函数设置的阈值进行比较。 比较结果表明存在时钟误差。 如果阈值设置为小于第二周期长度，则比较功能用于检测时钟毛刺。 如果阈值设置大于第二个周期，则比较功能用于检测时钟损耗。 比较的结果可以用于通过例如响应于时钟误差的检测在一个周期的长度上阻塞时钟信号中的逻辑状态变化来控制时钟信号的进一步处理。

    High performance phase locked loop for millimeter wave applications
    7.
    发明授权
    High performance phase locked loop for millimeter wave applications 有权

    公开(公告)号：US11563436B2

    公开(公告)日：2023-01-24

    申请号：US17863708

    申请日：2022-07-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Gagan Midha ,  Kallol Chatterjee ,  Anand Kumar ,  Ankit Gupta

    IPC: H03L7/089 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

    Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

    High performance phase locked loop for millimeter wave applications
    8.
    发明授权
    High performance phase locked loop for millimeter wave applications 有权

    公开(公告)号：US11431342B2

    公开(公告)日：2022-08-30

    申请号：US17521210

    申请日：2021-11-08

    Applicant: STMicroelectronics International N.V.

    Inventor： Gagan Midha ,  Kallol Chatterjee ,  Anand Kumar ,  Ankit Gupta

    IPC: H03L7/089 ,  H03L7/099 ,  H03L7/093 ,  H03L7/197

    Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

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