公开(公告)号：US20070170451A1

公开(公告)日：2007-07-26

申请号：US11645815

申请日：2006-12-26

Applicant: Nitin Bansal

Inventor： Nitin Bansal

IPC: H01L33/00

CPC classification number: H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator is in operation providing 1.2V supply to the core. If 1.2V is available on board, all 1.2V pads are bonded to the package pins and VDDCO pad is left unbonded. A weak pulldown ensures that the regulator is inoperational and the gate voltage of ballast transistor is pulled up. Now 1.2V pads directly get supply from the board through package pins and is provided to the core without suffering IR drop.

Abstract translation: 双板电压兼容性的芯片配置，包括镇流器I / O焊盘，调节器控制块和VDDCO焊盘。 如果板载1.8V，所有1.8V焊盘都连接到封装引脚，并且VDDCO焊盘与1.8V封装引脚双重连接。 这确保了稳压器在运行时向核心提供1.2V电源。 如果板载1.2V，则所有1.2V焊盘均焊接到封装引脚上，并且VDDCO焊盘未连接。 弱下拉确保调节器不工作，并且镇流器晶体管的栅极电压被拉高。 现在，1.2V焊盘直接通过封装引脚从板上供电，并提供给核心，而不会受到红外线损坏。

公开(公告)号：US07248066B2

公开(公告)日：2007-07-24

申请号：US11025854

申请日：2004-12-29

Applicant: Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

Inventor： Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

IPC: G01R31/28 ,  G01R27/28 ,  G01R19/00

CPC classification number: G01R31/2884 ,  G01R31/3004

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

Abstract translation: 一种用于独立于制造过程实现片上分析集成电路的一个或多个嵌入网络的电压和/或电流转换特性的装置。 所述装置包括用于提供可编程参考电压或电流的参考步长发生器（RSG），用于提供可编程延迟的步进延迟发生器（SDG）;在一个输入端接收参考步进发生器的输出的比较器（C） 在来自第二输入的被测节点的输出以及来自阶梯延迟发生器的锁存使能信号，并且响应于该比较而提供锁存的数字输出;以及控制器，其对参考步长发生器的操作进行调节，步骤 延迟发生器和锁存比较器提供瞬态响应测量。

公开(公告)号：US20070140326A1

公开(公告)日：2007-06-21

申请号：US11311024

申请日：2005-12-19

Applicant: Damanjit Singh

Inventor： Damanjit Singh

IPC: H04B17/00

CPC classification number: H04L1/08 ,  H04L1/0068

Abstract: A method employing an improved rate-matching algorithm used during transmission and reception of information packets involves performance of a complete process of puncturing or repetition in two steps. In the first step the action to be taken on each bit of the input register is calculated and is stored in the form of flag bits in flag register. In step 2, puncturing/repetition are performed on input bits and the output is stored in output register. Input bits can be processed in groups in step 2, reducing the number of steps required in the complete rate matching process.

Abstract translation: 使用在信息分组的发送和接收期间使用的改进的速率匹配算法的方法包括在两个步骤中执行穿孔或重复的完整过程。 在第一步中，计算输入寄存器每一位的动作，并以标志位的形式存储在标志寄存器中。 在步骤2中，对输入比特执行打孔/重复，输出被存储在输出寄存器中。 在步骤2中可以分组处理输入位，减少完整速率匹配过程中所需的步数。

公开(公告)号：US07227798B2

公开(公告)日：2007-06-05

申请号：US10679941

申请日：2003-10-06

Applicant: Anuj Gupta ,  Sanjeev Chopra

Inventor： Anuj Gupta ,  Sanjeev Chopra

IPC: G11C7/00

CPC classification number: G11C7/065

Abstract: An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.

Abstract translation: 具有形成锁存器的两个交叉耦合的反相器的改进的锁存型读出放大器电路，用于选择性地将锁存器连接到电源的电源耦合装置和用于选择性地将每个反相器的输入连接到补充位的位线耦合电路 线从内存阵列。 该电路被配置为通过提供延迟读出放大器使能信号来传递晶体管来延迟位线从读出放大器的断开直到闭锁动作完成，并且将两个晶体管加到 与常规锁存器的现有晶体管串联，用于校正锁存器的反相器的阈值电压之间的偏移。

公开(公告)号：US07205786B2

公开(公告)日：2007-04-17

申请号：US10832091

申请日：2004-04-26

Applicant: Adeel Ahmad

Inventor： Adeel Ahmad

IPC: H03K19/003

CPC classification number: H03K17/164

Abstract: A programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and a plurality of selectively enabled switching elements, at least a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements, and a selection means that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and slew rate.

Abstract translation: 一种可编程输出缓冲器，为给定的噪声限制提供可变的驱动强度和压摆率，其包括产生缓冲器的输出的驱动器级和多个有选择地使能的开关元件，至少一个提供多个可选开关元件的预驱动级， 使所选择的驱动级开关元件和选择装置能够以期望的顺序使所需的预驱动开关元件提供期望的驱动强度和压摆率。

公开(公告)号：US07199638B2

公开(公告)日：2007-04-03

申请号：US11017409

申请日：2004-12-20

Applicant: Hari Bilash Dubey ,  Anshu Vij

Inventor： Hari Bilash Dubey ,  Anshu Vij

IPC: H03L5/00

CPC classification number: H03K19/018528

Abstract: A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive a low voltage input signal and to control current in the translated high level voltage signal. The translator further provides a differential amplifier arrangement for receiving the low level voltage input signal and provides feedback signals to the transistorized arrangement thereby outputting a high level voltage translated signal.

Abstract translation: 具有最小功率消耗和减小面积的高速电压电平转换器，特别是在0.1微米范围内，包括用于接收低电压输入信号并控制转换的高电平电压信号中的电流的晶体管结构。 转换器还提供用于接收低电平电压输入信号并将反馈信号提供给晶体管结构的差分放大器装置，从而输出高电平电压转换信号。

公开(公告)号：US07157936B2

公开(公告)日：2007-01-02

申请号：US10347139

申请日：2003-01-17

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: H01L25/00

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 提供了一种方法和改进的FPGA装置，用于在核心逻辑功能中使得能够选择性地部署IO单元中的未使用的触发器或其他电路元件以及查找表（LUT）中的未使用的解码器或其他电路元件，包括用于 有选择地从IO垫电路或所述LUT电路断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或它们之间，以提供独立配置的功能。

公开(公告)号：US07154299B2

公开(公告)日：2006-12-26

申请号：US10407802

申请日：2003-04-04

Applicant: Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

公开(公告)号：US20060250169A1

公开(公告)日：2006-11-09

申请号：US11413630

申请日：2006-04-28

Applicant: Puneet Sareen ,  Sashi Singh

Inventor： Puneet Sareen ,  Sashi Singh

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/0812

Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.

Abstract translation: 用于在时钟的上升/下降沿启用占空比锁定的装置包括接收门控输入时钟的计数器。 锁定检测器接收用于产生控制信号的输入时钟。 地址解码器连接到计数器以产生一组选择信号。 第一多路复用器包括连接以接收选择信号的选择线。 多个延迟链提供具有连接到第一多路复用器的第一延迟链的多个输出抽头。 第二多路复用器连接到多个延迟链中的一个，其选择线是硬连线的。 锁存器连接到第一多路复用器和第二多路复用器的输出端，用于提供输出。

公开(公告)号：US07130230B2

公开(公告)日：2006-10-31

申请号：US10922825

申请日：2004-08-20

Applicant: Mohit Jain ,  Danish Hasan Syed

Inventor： Mohit Jain ,  Danish Hasan Syed

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C29/38

Abstract: An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, including a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial bit stream; a bit transition detector that detects and determines the address of each bit transition in the serial bit stream; a state machine that generates bit addresses for each expected transition in the serial bit stream; and an analyser that compares expected transition bit addresses with detected transition addresses and declares a BIST failure if expected and detected transition addresses do not match at any point in the bit stream.

Abstract translation: 用于内容可寻址存储器（CAM）设备的改进的内置自测（BIST）架构，包括用于读出作为串行比特流的CAM单元的匹配线的内容的位扫描器; 一个位转换检测器，用于检测和确定串行比特流中每个位转换的地址; 状态机，为串行比特流中的每个预期转换生成位地址; 以及分析器，将预期的转换位地址与检测到的转换地址进行比较，并在预期的情况下声明BIST故障，并且检测到的转换地址在位流中的任何位置都不匹配。