利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.014 秒)

    Architecture for programmable logic device
    2.
    发明授权
    Architecture for programmable logic device 有权

    公开(公告)号：US07154299B2

    公开(公告)日：2006-12-26

    申请号：US10407802

    申请日：2003-04-04

    申请人： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    发明人： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

    Low power clock distribution scheme
    3.
    发明授权
    Low power clock distribution scheme 有权
    低功率时钟分配方案

    公开(公告)号：US06879185B2

    公开(公告)日：2005-04-12

    申请号：US10407801

    申请日：2003-04-04

    申请人： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    发明人： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

    IPC分类号： H03K19/177 ,  H03K19/00

    CPC分类号： H03K19/1774 ,  H03K19/17784

    摘要： An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

    摘要翻译： 一种包含一个或多个数字同步顺序逻辑块的电子电路，其中至少一个在操作期间被选择或取消选择。 电子电路包括一种降低功耗的改进的时钟分配方案，包括识别装置，用于确定每个所述可取消同步顺序逻辑块的选择/取消选择状态，耦合到禁用装置，用于禁止每个取消选择的同步顺序逻辑块的时钟输入。

    High performance interconnect architecture for field programmable gate arrays
    4.
    发明授权
    High performance interconnect architecture for field programmable gate arrays 有权
    用于现场可编程门阵列的高性能互连架构

    公开(公告)号：US07030648B2

    公开(公告)日：2006-04-18

    申请号：US10739395

    申请日：2003-12-18

    申请人： Ankur Bal ,  Namerita Khanna

    发明人： Ankur Bal ,  Namerita Khanna

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

    摘要翻译： 本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

    Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices
    5.
    发明授权
    Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices 失效
    在配置可编程逻辑器件期间重新加载错误配置数据帧的方法和装置

    公开(公告)号：US07350134B2

    公开(公告)日：2008-03-25

    申请号：US10667199

    申请日：2003-09-18

    申请人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    发明人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    IPC分类号： G11C29/00 ,  G06F11/00

    CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    摘要： An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ‘n’. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

    摘要翻译： 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。

    Programmable logic devices
    6.
    发明申请
    Programmable logic devices 有权
    可编程逻辑器件

    公开(公告)号：US20050172070A1

    公开(公告)日：2005-08-04

    申请号：US11005247

    申请日：2004-12-06

    申请人： Davinder Aggarwal ,  Ashish Goel ,  Namerita Khanna

    发明人： Davinder Aggarwal ,  Ashish Goel ,  Namerita Khanna

    IPC分类号： G06F13/28 ,  H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/1776

    摘要： An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

    摘要翻译： 改进的可编程逻辑器件在块存储器的配置中提供增加的效率和增强的灵活性，并且包括一个或多个存储器块和接收待加载到存储器块中的数据的垂直移位寄存器。 PLD还提供用于选择要存储接收到的数据的存储器块中的存储器单元的选择装置，以及用于控制数据在存储块中的加载的控制块。 选择装置包括与地址解码器的输入连接的地址计数器，以便能够选择存储块中的地址。

    Processing Configuration Data Frames
    7.
    发明申请
    Processing Configuration Data Frames 有权
    处理配置数据帧

    公开(公告)号：US20080215935A1

    公开(公告)日：2008-09-04

    申请号：US12032448

    申请日：2008-02-15

    申请人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    发明人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    摘要： In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

    摘要翻译： 在至少一些实施例中，可编程逻辑设备（PLD）被配置为结合阈值使用计数器，以确定如果遇到错误，配置数据帧是否被重新加载到帧寄存器中。 在至少其他实施例中，可编程逻辑器件（PLD）被配置为将配置数据帧顺序地加载到帧寄存器中，在顺序加载期间检查配置数据帧中的错误，并且在顺序加载期间校正错误，而不重新加载一个或多个先前 加载不同的配置数据帧。

    Processing configuration data frames
    8.
    发明授权
    Processing configuration data frames 有权
    处理配置数据帧

    公开(公告)号：US07774682B2

    公开(公告)日：2010-08-10

    申请号：US12032448

    申请日：2008-02-15

    申请人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    发明人： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    摘要： In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

    摘要翻译： 在至少一些实施例中，可编程逻辑设备（PLD）被配置为结合阈值使用计数器，以确定如果遇到错误，配置数据帧是否被重新加载到帧寄存器中。 在至少其他实施例中，可编程逻辑器件（PLD）被配置为将配置数据帧顺序地加载到帧寄存器中，在顺序加载期间检查配置数据帧中的错误，并且在顺序加载期间校正错误，而不重新加载一个或多个先前 加载不同的配置数据帧。

    Programmable logic devices
    9.
    发明授权
    Programmable logic devices 有权
    可编程逻辑器件

    公开(公告)号：US07606969B2

    公开(公告)日：2009-10-20

    申请号：US11005247

    申请日：2004-12-06

    申请人： Davinder Aggarwal ,  Ashish Kumar Goel ,  Namerita Khanna

    发明人： Davinder Aggarwal ,  Ashish Kumar Goel ,  Namerita Khanna

    IPC分类号： G06F13/00

    CPC分类号： H03K19/17748 ,  H03K19/1776

    摘要： An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

    摘要翻译： 改进的可编程逻辑器件在块存储器的配置中提供增加的效率和增强的灵活性，并且包括一个或多个存储器块和接收待加载到存储器块中的数据的垂直移位寄存器。 PLD还提供用于选择要存储接收到的数据的存储器块中的存储器单元的选择装置，以及用于控制数据在存储块中的加载的控制块。 选择装置包括与地址解码器的输入连接的地址计数器，以便能够选择存储块中的地址。