公开(公告)号：US10942876B1

公开(公告)日：2021-03-09

申请号：US16683300

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Carl Ramey ,  Christopher Jackson ,  Diane Orf ,  Matt Orsini ,  Michael Cotsford ,  Mark B. Rosenbluth ,  Rui Xu

IPC: G06F13/20 ,  G06F9/30 ,  G06F13/42

Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of the tiles.

公开(公告)号：US20210044461A1

公开(公告)日：2021-02-11

申请号：US16943615

申请日：2020-07-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Matan Groen ,  Chen Gaist ,  Hananel Faig

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

Abstract: A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N′

公开(公告)号：US20210007240A1

公开(公告)日：2021-01-07

申请号：US16502686

申请日：2019-07-03

Applicant: Mellanox Technologies, Ltd.

Inventor： Avner Badihi ,  Eyal Babish

IPC: H05K7/20 ,  H05K7/14 ,  H05K7/10

Abstract: A universal replaceable fan unit and method of reversing an airflow direction of a universal replaceable fan unit is provided. The universal replaceable fan unit includes a fan assembly designed to create an airflow from an intake end to an output end. The universal replaceable fan unit also includes a fan mounting that receives and secures the fan assembly in an operable position. The fan mounting includes a frame member and a securing member. The fan mounting is designed to allow the fan assembly to be moved between a first position defining a first airflow direction and a second position defining a second airflow direction. The first airflow direction is opposite the second airflow direction. The universal replaceable fan unit further includes an electrical connector removably attached to the fan assembly. The electrical connector allows electricity to be provided to the fan assembly for operation.

公开(公告)号：US10887252B2

公开(公告)日：2021-01-05

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: G06F15/167 ,  H04L12/879 ,  H04L12/883 ,  H04L12/931 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

公开(公告)号：US20200348944A1

公开(公告)日：2020-11-05

申请号：US16400047

申请日：2019-05-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Oren Ish-Am ,  Guy Heller ,  Noam Cohen

IPC: G06F9/445 ,  G06F11/26 ,  G06F13/42 ,  G06F13/40

Abstract: An electronic device includes a processor, a Nonvolatile Memory (NVM), and a Programmable Logic Device (PLD). The NVM stores loadable shell image and user image. The shell image supports communication with the processor, and each of the shell and user images implements a bus client for communication with a host in accordance with a bus protocol. The PLD connects to the processor and to the NVM. Upon initialization, the PLD is configured to load and run the shell image, to receive from the processor, by the shell image, an indication for selecting between the shell and user images, and when the indication selects the user image, to load the user image and run the loaded user image. The process of sequential loading of the shell and user images completes before the host concludes attempting to enumerate the bus client of the user image, in accordance with the bus protocol.

公开(公告)号：US10824501B2

公开(公告)日：2020-11-03

申请号：US16240816

申请日：2019-01-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Itkin ,  Ahmad Atamlh

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/0895 ,  G06F12/10 ,  G06F21/57 ,  G06F9/455 ,  H04L29/06

Abstract: Apparatus having a firmware memory storing firmware, a cache memory loading at least part of the firmware for execution by a processor, and a firmware checking engine having a defined syndrome storage location and performing the following iteratively on cache line entries associated with the firmware stored in the cache memory: choose a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare a content of the cache line entry to a content of a corresponding address in the firmware stored in the firmware memory, and produce an integrity result indicating whether integrity of the apparatus has been compromised.

公开(公告)号：US20200314181A1

公开(公告)日：2020-10-01

申请号：US16827912

申请日：2020-03-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

IPC: H04L29/08

Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

公开(公告)号：US10778406B2

公开(公告)日：2020-09-15

申请号：US16199312

申请日：2018-11-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Chen Gaist ,  Ran Ravid ,  Aviv Berg ,  Lavi Koch

IPC: H04L7/04

Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

公开(公告)号：US20200284999A1

公开(公告)日：2020-09-10

申请号：US16792331

申请日：2020-02-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Hen Seri ,  Andrey Ger

IPC: G02B6/38

Abstract: In one embodiment, an apparatus, includes an MPO connector including a main body including a connector interface to be reversibly connected to an MPO interface of an optical module, locking elements configured to lock the MPO connector with the optical module, a pull-to-release housing configured to expose the locking elements to allow removal of the MPO connector from the optical module, and an elongated channel, wherein the pull-to release housing and main body define a slot therebetween in which to retract the pull-to-release housing, and a T-shape locking key including a top section and a flexible elongated section extending from the top section, the elongated section configured to be inserted into the channel and the top section configured to rest in the slot so that retraction of the pull-to-release housing is restricted by the top section, thereby preventing unlocking of the MPO connector from the optical module.

公开(公告)号：US10764194B2

公开(公告)日：2020-09-01

申请号：US15836869

申请日：2017-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Michael Kagan ,  Noam Bloch

IPC: G06F13/30 ,  H04L12/851 ,  H04L29/00 ,  H04L29/08

Abstract: A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.