公开(公告)号：US5307477A

公开(公告)日：1994-04-26

申请号：US59715

申请日：1993-05-10

申请人： George S. Taylor ,  P. Michael Farmwald ,  Timothy P. Layman ,  Huy X. Ngo ,  Allen W. Roberts

发明人： George S. Taylor ,  P. Michael Farmwald ,  Timothy P. Layman ,  Huy X. Ngo ,  Allen W. Roberts

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0891 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/1045

摘要： A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

摘要翻译： 一种用于包括两个主高速缓冲存储器的计算机系统的两级缓存存储器系统，一个用于存储指令，一个用于存储数据。 该系统还包括用于存储指令和数据的二级高速缓冲存储器。 主缓存和辅助缓存每个使用自己的单独的标签目录。 主缓存使用采用虚拟标签和虚拟地址的虚拟寻址方案。 二级缓存采用使用虚拟标签和部分物理地址的混合寻址方案。 主缓存和副缓存并行运行，除非较大和较慢的二级缓存正在执行先前的操作。 只有在主缓存和副缓存中遇到“未命中”，系统处理器才能访问主内存。

公开(公告)号：US5301153A

公开(公告)日：1994-04-05

申请号：US893156

申请日：1992-06-03

申请人： Larry D. Johnson

发明人： Larry D. Johnson

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/848

摘要： A redundant array element or signal line is selectively added and an defective array element or signal line is eliminated by the method and apparatus of the present invention. A multiplexor receives an input signal and a neighboring input signal and outputs one of these two input signals in response to a control signal. A fuse is provided in connection with each output line and configured such that if the fuse is unblown, the device selects the same input as was selected by its upstream neighbor. If a fuse if blown, the multiplexor will select the second input and will output a control signal to its downstream neighbor causing the downstream neighbor to also output its second input line and to output a control signal to its downstream neighbor to select the second input line. The substitution of a redundant element or line is achieved by blowing a single fuse and the circuitry adds only a single mux delay to the critical path.

摘要翻译： 选择性地添加冗余阵列元件或信号线，并且通过本发明的方法和装置消除有缺陷的阵列元件或信号线。 多路复用器接收输入信号和相邻输入信号，并响应于控制信号输出这两个输入信号中的一个。 提供与每个输出线连接的保险丝，并且被配置为使得如果保险丝未被吹出，则该设备选择与其上游邻居所选择的相同的输入。 如果熔丝熔断，则多路复用器将选择第二个输入，并向其下游邻居输出一个控制信号，导致下游邻居也输出其第二个输入线，并向其下游邻居输出一个控制信号，以选择第二条输入线 。 冗余元件或线路的替换是通过吹一个熔丝来实现的，并且该电路仅对关键路径增加单个多路延迟。

公开(公告)号：US5285116A

公开(公告)日：1994-02-08

申请号：US573926

申请日：1990-08-28

申请人： Albert Thaik

发明人： Albert Thaik

IPC分类号： H03K17/14 ,  H03K17/16 ,  H03K19/017

CPC分类号： H03K17/145 ,  H03K17/164

摘要： A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the digital control signal values for the rest. The switching delay is controlled by referencing the one output buffer's delay to a clock cycle (e.g., 0.75 T or T, where T equals the clock cycle period). The digital control signal values which define the delay with reference to the clock cycle also determine the di/dt for the output buffers. As process or operating conditions vary, the control signal values change to maintain the delay in the prescribed relation to the clock cycle. Accordingly, the absolute di/dt values change. Thus, the output signal is available by the time needed (e.g., 0.75 T), while the di/dt is varied to an optimum setting based on the absolute delay time. As a result, the variation in di/dt from fastest conditions to slowest conditions is smaller enabling an increased ability to conform to noise margin requirements for increasingly faster systems. Accordingly, a low-noise high-speed output buffer and method of controlling the same is provided.

摘要翻译： 低噪声高速输出缓冲器接收用于改变缓冲器的开关延迟和di / dt的数字控制信号。 对于多个输出缓冲器，使用一个缓冲器来确定其余的数字控制信号值。 通过将一个输出缓冲器的延迟参考到时钟周期（例如，0.75T或T，其中T等于时钟周期周期）来控制开关延迟。 参考时钟周期定义延迟的数字控制信号值也决定了输出缓冲器的di / dt。 随着过程或操作条件的变化，控制信号值发生变化，以保持与时钟周期规定关系的延迟。 因此，绝对di / dt值发生变化。 因此，输出信号可用于所需时间（例如，0.75T），而di / dt基于绝对延迟时间变化到最佳设置。 因此，从最快条件到最慢条件的di / dt的变化较小，能够提高符合越来越快的系统的噪声容限要求的能力。 因此，提供了低噪声高速输出缓冲器及其控制方法。

公开(公告)号：US5179670A

公开(公告)日：1993-01-12

申请号：US444633

申请日：1989-12-01

申请人： Paul M. Farmwald ,  Timothy S.-C. Fu

发明人： Paul M. Farmwald ,  Timothy S.-C. Fu

IPC分类号： G06F13/40

CPC分类号： G06F13/4068

摘要： A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one or more pulses from upstream sends that many plus one pulses downstream and then sends a one pulse upstream. Each unit then transmits upstream whatever it receives from downstream. The number of pulses received from upstream provide the slot number. The total number of pulses received from upstream and downstream provide the total number of units.

摘要翻译： 一种槽确定机构，其中多个总线单元沿总线建立其位置以及总线上的单元总数。 这些单元以双向菊花链连接。 下游向单元1（上游单元）发送单周期复位脉冲。 从上游接收一个或多个脉冲的每个单元在下游发送许多加一个脉冲，然后向上发送一个脉冲。 然后，每个单元向上游发送从下游接收的任何数据。 从上游接收的脉冲数提供槽号。 从上游和下游接收的总脉冲数总数为单位数。

公开(公告)号：US5111464A

公开(公告)日：1992-05-05

申请号：US444639

申请日：1989-12-01

申请人： Paul M. Farmwald ,  Timothy S. Fu

发明人： Paul M. Farmwald ,  Timothy S. Fu

IPC分类号： G06F12/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/1048

摘要： Error reporting circuitry interrupts the CPU on the occurrence of a single bit memory error only when the chip member causing the error is different from the chip number that caused the previous error.

公开(公告)号：US4814976A

公开(公告)日：1989-03-21

申请号：US945486

申请日：1986-12-23

申请人： Craig C. Hansen ,  Thomas J. Riordan

发明人： Craig C. Hansen ,  Thomas J. Riordan

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F12/04

CPC分类号： G06F9/30043 ,  G06F12/04 ,  G06F9/3816

摘要： In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.

摘要翻译： 在RISC设备中，提供了一组四个指令，允许加载或存储未对齐的引用。 指令重叠以减少设备的总体执行时间。 还提供用于执行指令集的电路。