公开(公告)号：US07208981B1

公开(公告)日：2007-04-24

申请号：US10907904

申请日：2005-04-20

申请人： Ramsin M. Ziazadeh ,  Vijaya Ceekala ,  Matthew James Webb ,  James B. Wieser

发明人： Ramsin M. Ziazadeh ,  Vijaya Ceekala ,  Matthew James Webb ,  James B. Wieser

IPC分类号： H03K5/22

CPC分类号： H04L25/028 ,  H04L1/24 ,  H04L25/0272

摘要： A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.

摘要翻译： 提供了一种电路和方法，用于对集成差分信号发生器电路的输出信号幅值进行内置测试。 根据一个实施例，经由多个参考电极接收第一上参考电压和第二上参考电压和第二上基准电压和下参考电压，其中：第一和上参考电压之间的差包括第一差幅度; 第二上参考电压和下参考电压之间的差包括第二差值; 并且第一差值幅度大于第二差值幅度。 测试信号发生器电路提供具有各自相对的信号状态的多个二进制信号。 耦合到测试信号发生器电路并响应于多个二进制信号的差分信号发生器电路提供具有与相应二进制信号状态的相应序列相关的相应幅度的多个差分信号。 耦合到多个参考电极和差分信号发生器电路并且响应于第一和第二上参考信号和下参考信号和多个差分信号的信号比较电路提供多个测试信号，其中各测试信号状态指示 差分信号幅度中的各个是否在限定为小于第一差分幅度并大于第二差值的范围内。

公开(公告)号：US07197331B2

公开(公告)日：2007-03-27

申请号：US10334158

申请日：2002-12-30

申请人： Tasos Anastasakos ,  Senaka Balasuriya ,  Michael Van Wie

发明人： Tasos Anastasakos ,  Senaka Balasuriya ,  Michael Van Wie

IPC分类号： H04B1/38

CPC分类号： G10L15/30 ,  H04M1/72566 ,  H04M1/72572 ,  H04M2250/74

摘要： A method and apparatus for selective distributed speech recognition includes an embedded speech recognition engine (104) and a dialog manager (102), such as a browser, coupled to the embedded speech recognition engine (104). The method and apparatus further includes the dialog manager (102) being operably couple able to at least one external speech recognition engine (106), such as a WLAN speech recognition engine (108) or a network speech recognition engine (110). The method and apparatus further includes preference information (114), environment information (112) and a speech input (116) all provided to the dialog manager (102). The dialog manager (102), in response to the preference information (114) and the environment information (112), provides the speech input (116) to the embedded speech recognition engine (104), the WLAN speech recognition engine (108) or the network speech recognition engine (110).

摘要翻译： 用于选择性分布式语音识别的方法和装置包括耦合到嵌入式语音识别引擎（104）的嵌入式语音识别引擎（104）和对话管理器（102），诸如浏览器。 所述方法和装置还包括对话管理器（102），其可操作地耦合到至少一个外部语音识别引擎（106），诸如WLAN语音识别引擎（108）或网络语音识别引擎（110）。 所述方法和装置还包括全部提供给对话管理器（102）的偏好信息（114），环境信息（112）和语音输入（116）。 对话管理器（102）响应于偏好信息（114）和环境信息（112），将语音输入（116）提供给嵌入式语音识别引擎（104），WLAN语音识别引擎（108）或 网络语音识别引擎（110）。

公开(公告)号：US07174507B2

公开(公告)日：2007-02-06

申请号：US10360864

申请日：2003-02-10

申请人： Catherine Marie Baudin ,  Michel Vladimir Manago ,  Olivier Camille Madec

发明人： Catherine Marie Baudin ,  Michel Vladimir Manago ,  Olivier Camille Madec

IPC分类号： G06F15/00

CPC分类号： G06F17/30616 ,  G06F17/3043

摘要： A method, system, and computer program product for obtaining structured data from text includes inputting text to be transformed into structured data, defining at least one criterion relating to content of the text, applying a first matching method to the text to identify a value in the text for each of the criterion, and applying a second matching method to the text to identify a value in the text for each of the criterion that the first matching method fails to identify a value for. Each of the criterion is then associated with a value obtained by the first or second matching method to create at least one criterion-value pair, and structured data is created based on the at least one criterion-value pair. The first matching method has a higher reliability than the second matching method.

摘要翻译： 用于从文本获得结构化数据的方法，系统和计算机程序产品包括输入要转换成结构化数据的文本，定义与文本内容有关的至少一个标准，向文本应用第一匹配方法以识别文本中的值 用于每个标准的文本，以及将第二匹配方法应用于文本，以识别第一匹配方法无法识别值的每个标准的文本中的值。 然后将每个标准与通过第一或第二匹配方法获得的值相关联以创建至少一个标准值对，并且基于至少一个标准 - 值对创建结构化数据。 第一匹配方法具有比第二匹配方法更高的可靠性。

公开(公告)号：US07161430B1

公开(公告)日：2007-01-09

申请号：US10957953

申请日：2004-10-04

申请人： Arlo Aude

发明人： Arlo Aude

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions.

摘要翻译： 用于环形振荡器的低压折叠金属氧化物半导体场效应晶体管（MOSFET）放大器电路。 通过具有选择性协调的晶体管偏置和沟道尺寸的电路拓扑实现在降低的最小电源电压下的操作。

公开(公告)号：US07145564B1

公开(公告)日：2006-12-05

申请号：US09585217

申请日：2000-06-01

申请人： Alexander C. Vlachos ,  Vineet Goel

发明人： Alexander C. Vlachos ,  Vineet Goel

IPC分类号： G06T15/00

CPC分类号： G06T17/20 ,  G06T15/80

摘要： A method and apparatus for performing tessellation lighting operations for video graphics primitives in a video graphics system is presented. When the vertex parameters corresponding to the vertices of a video graphics primitive are received, a tessellation operation is performed such that a number of component primitives are generated. The vertex parameters corresponding to the vertices of the component primitives are then calculated utilizing the vertex parameters for the original video graphics primitive. Such calculation operations include determining a corresponding normal vector for each component primitive vertex. Each of the component primitives is then individually processed. Such processing may include calculating the lighting effects for each component primitive and performing additional processing operations that generate pixel fragments for the primitive. The resulting pixel fragments are blended with image data stored in a frame buffer, where the image data is used in generating a displayed image.

摘要翻译： 提出了一种用于对视频图形系统中的视频图形图元执行镶嵌照明操作的方法和装置。 当接收到对应于视频图形原语的顶点的顶点参数时，执行细分操作，使得生成多个组件基元。 然后使用原始视频图形原语的顶点参数计算与组件基元的顶点对应的顶点参数。 这样的计算操作包括确定每个分量原始顶点的相应法向量。 然后单独处理每个组件原语。 这样的处理可以包括计算每个组件原语的照明效果并且执行生成图元的像素片段的附加处理操作。 所得到的像素碎片与存储在帧缓冲器中的图像数据混合，其中图像数据用于生成显示的图像。

公开(公告)号：US07132887B1

公开(公告)日：2006-11-07

申请号：US10957976

申请日：2004-10-04

申请人： Arlo Aude

发明人： Arlo Aude

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/513 ,  H03F2203/45326 ,  H03F2203/45652

摘要： A low voltage semi-folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions.

摘要翻译： 用于环形振荡器的低压半折叠金属氧化物半导体场效应晶体管（MOSFET）放大器电路。 通过具有选择性协调的晶体管偏置和沟道尺寸的电路拓扑实现在降低的最小电源电压下的操作。

公开(公告)号：US07130425B2

公开(公告)日：2006-10-31

申请号：US11175882

申请日：2005-07-06

申请人： David A. Strasser ,  Edwin Pang ,  Gabriel Z. Varga

发明人： David A. Strasser ,  Edwin Pang ,  Gabriel Z. Varga

IPC分类号： H04L9/00

CPC分类号： H04N21/4181 ,  H04L9/0841 ,  H04L9/0891 ,  H04L2209/605 ,  H04N7/1675 ,  H04N21/4367

摘要： A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus. The locally exchanged public keys are shorter in length than those used between the CPU and POD to produce the original CP key.

摘要翻译： 由POD等发送源用于加密诸如音频和/或视频信息的内容的复制保护（CP）密钥由与第一处理器相关联的第一密钥生成器导出，并且由第一处理器本地加密使用 本地生成的总线加密密钥，以产生通过本地不安全总线发送到诸如图形处理器的第二处理器的总线加密CP密钥。 第二处理器使用解密引擎解密总线加密复制密钥以获得CP密钥。 第二处理器接收加密的内容，并且在一个实施例中，还使用相同的解密引擎来解密加密的内容。 第一和第二处理器在本机之间本地交换公共密钥本地导出用于在通过不安全总线发送之前对CP密钥进行加密的总线加密密钥，并且在通过总线发送之后解密加密的CP密钥。 本地交换的公钥的长度要比在CPU和POD之间使用的公钥短，以产生原始的CP密钥。

公开(公告)号：US07130366B2

公开(公告)日：2006-10-31

申请号：US10290674

申请日：2002-11-08

申请人： Abhijit Phanse ,  Abhijit G. Shanbhag

发明人： Abhijit Phanse ,  Abhijit G. Shanbhag

IPC分类号： H04B1/00

CPC分类号： H04L25/03057 ,  H04B10/6971 ,  H04L25/03038 ,  H04L25/03878 ,  H04L2025/03624 ,  H04L2025/03656 ,  H04L2025/037

摘要： A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

公开(公告)号：US07113194B2

公开(公告)日：2006-09-26

申请号：US09772789

申请日：2001-01-30

申请人： Andrzej S. Mamona ,  Oleksandr Khodorkovsky

发明人： Andrzej S. Mamona ,  Oleksandr Khodorkovsky

IPC分类号： G06T15/00

CPC分类号： G06T3/60 ,  G06T15/04

摘要： A method and apparatus utilizes a three dimensional rendering engine to rotate an image based on user selected or otherwise determined screen orientation. A vertex coordinate transformation is defined for a rotated destination image. The source image is used as a texture for texture mapping during rendering operation to produce rotated image. In one embodiment, a separate set of software instructions is used for each orientation mode. Accordingly, a non-pixel by pixel based 3D rotation may be carried out using a 3D rendering engine to avoid a single parameter based seriatim pixel by pixel based orientation.

公开(公告)号：US07109987B2

公开(公告)日：2006-09-19

申请号：US10790952

申请日：2004-03-02

申请人： Vineet Goel ,  Stephen L. Morein ,  Robert Scott Hartog

发明人： Vineet Goel ,  Stephen L. Morein ,  Robert Scott Hartog

IPC分类号： G06T15/30

CPC分类号： G06T17/20 ,  G06T15/005 ,  G06T2200/28

摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

摘要翻译： 用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。 在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。 所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点 着色器产生细分因素。 将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。