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公开(公告)号：US20080252407A1
公开(公告)日：2008-10-16
申请号：US12088730
申请日：2006-10-04
申请人： Alma Anderson
发明人： Alma Anderson
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , Y10T29/4902
摘要： According to one example embodiment, an inductive element is used for power-conversion applications. The inductive element includes a substrate (188) having a first metal layer (190) on the substrate having a thickness greater than one micrometer and arranged as a first set of adjacent non-intersecting conducting segments. There is a ferromagnetic-based body (192) located on the first metal layer that has a ferromagnetic inner core area. At least one other metal layer (198) is on the ferromagnetic-based body and arranged as a second set of adjacent non-intersecting conducting segments. A plurality of conductive vias (194) are located in the ferromagnetic-based body and are arranged to connect respective ones of the first set of adjacent non-intersecting conducting segments to respective ones of the second set of adjacent non-intersecting conducting segments therein providing a contiguous conductive wrap around the inner core area. Other example embodiments include layer thicknesses in excess of those used in normal semiconductor processing.
摘要翻译： 根据一个示例实施例，电感元件用于功率转换应用。 电感元件包括在衬底上具有大于1微米厚度的第一金属层（190）的衬底（188），并且被布置为第一组相邻的不相交的导电段。 位于第一金属层上的铁磁体（192）具有铁磁内芯区域。 至少一个其它金属层（198）位于铁磁体上并且被布置为第二组相邻的非相交导电段。 多个导电通孔（194）位于铁磁体中，并且被布置成将第一组相邻的不相交的导电段中的相应的第一组相邻的不相交的导电段相互连接， 围绕内芯区域的连续的导电包裹物。 其他示例性实施例包括超过在正常半导体处理中使用的层厚度的层厚度。
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公开(公告)号：US5654858A
公开(公告)日：1997-08-05
申请号：US332621
申请日：1994-10-31
申请人： Brian C. Martin , Alma Anderson , Harold G. Hanson
发明人： Brian C. Martin , Alma Anderson , Harold G. Hanson
IPC分类号： H02H9/04 , H03K17/082 , H03K19/003 , H02H9/00
CPC分类号： H03K19/00315 , H03K17/0822 , H03K2217/0018
摘要： Output overvoltage protection circuitry for circuits operating at low voltages (e.g., 3 v) interfacing to a higher voltage operating circuit (e.g., 5 v bus). To prevent problems with a pull-up PMOS device at the output when the bus is pulled-up to the higher voltage, a voltage node is provided in the circuit which follows the output voltage or the low supply voltage, whichever is higher, and a sub-circuit is provided to generate logic signals indicating when the bus is pulled too high. The PMOS device is then shut-down to prevent damage to the circuit.
摘要翻译： 用于在较高电压工作电路（例如5 V总线）上连接的低电压（例如3 v）工作的电路的输出过压保护电路。 为了防止当总线上拉到较高电压时输出端上拉PMOS器件出现问题，电路中提供了一个电压节点，该电压节点靠近输出电压或低电源电压（以较高者为准），以及 提供子电路以产生指示总线被拉得太高的逻辑信号。 然后关闭PMOS器件以防止损坏电路。
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公开(公告)号：US20100237919A1
公开(公告)日：2010-09-23
申请号：US12294982
申请日：2007-03-31
申请人： Joseph Rutkowski , Alma Anderson
发明人： Joseph Rutkowski , Alma Anderson
IPC分类号： H03K5/12
CPC分类号： H03K19/00361 , H03K17/166
摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.
摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）将反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。
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14.发明申请公开(公告)号：US20100205326A1
公开(公告)日：2010-08-12
申请号：US12761662
申请日：2010-04-16
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.
摘要翻译： 与一个示例性实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统使用I2C串行总线并行编程并行从设备。 至少两个从设备在数据传输总线上并联耦合，并配置为使用通信协议通过串行数据线加载串行数据。 每个从设备包括可编程配置寄存器，其被配置为使用通信协议来编程以选择多个可选择的从设备配置中的一个。 可选择的从设备配置之一使得至少两个从设备并行加载串行数据，另一个可选择的从设备配置使得至少两个从设备一次一个地加载。
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公开(公告)号：US07747802B2
公开(公告)日：2010-06-29
申请号：US11913063
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers in the second configuration.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统将逻辑值的可编程加载并入到并行从设备寄存器中。 通信系统包括具有两个或更多个寄存器的从设备，每个寄存器具有两个或多个位，每个寄存器被配置为在第一配置中通过数据传输总线加载根据通信协议接收的数据，并且加载单个 第二配置中的多个位的逻辑值。 根据通过数据传输总线的通信协议，可编程配置寄存器被配置为在第二配置中选择两个或更多个寄存器。
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公开(公告)号：US07606956B2
公开(公告)日：2009-10-20
申请号：US11913057
申请日：2006-05-01
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统并入或并行地并入从属设备输出组的可编程更新。 通信系统包括两个或更多个从设备和/或具有两个或更多个输出驱动器组的从设备。 每个从设备接收串行数据并提供从串行数据组装的数据字。 使用通信协议对每个从设备中的可编程寄存器进行编程，以选择一个或多个从设备配置。 基于每个从设备，两个或更多个从设备和/或两个或更多个输出驱动器组中的每一个依次或与两个或更多个从设备中的其他设备和/或两个或更多个输出驱动器组配合地更新 配置由其可编程寄存器选择。
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公开(公告)号：US20080215779A1
公开(公告)日：2008-09-04
申请号：US11913061
申请日：2006-05-01
IPC分类号： G06F13/18
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems (100), using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to request service from a master device (130) involve detecting a condition that asserts a request for service signal (162), at a common node (150) independent from the serial data transfer bus, to a master device of the bus. The request for service is latched (164), within the slave, such that the request for service remains asserted regardless of a change in the detected condition. The request for service is de-asserted (166) in response to interrogation of the slave, using the serial data transfer bus, by the master device. Devices may be configured as general purpose Input/Output devices, CODEC arrangements, or other slave devices, and may conform to I2C and/or SMBus serial communication specifications.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统（100）包括锁存的服务请求。 用于从主设备（130）请求服务的一个或多个从设备的方法涉及检测在与串行数据传输总线独立的公共节点（150）向主设备请求服务信号（162）的状态 总线设备 服务请求在从机中被锁存（164），使得服务请求保持有效，而不管检测到的状况如何变化。 响应于由主设备使用串行数据传输总线询问从设备，服务请求被取消（166）。 设备可以配置为通用输入/输出设备，CODEC布置或其他从设备，并且可以符合I2C和/或SMBus串行通信规范。
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18.发明申请公开(公告)号：US20080195764A1
公开(公告)日：2008-08-14
申请号：US11913065
申请日：2006-05-01
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems (100,300), using a serial data transfer bus having a serial data line (110) and a clock line (120) used to implement a communications protocol, incorporate programming of parallel slave devices (320,330,340,350) concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.
摘要翻译： 与一个示例性实施例一致，使用用于实现通信协议的具有串行数据线（110）和时钟线（120）的串行数据传输总线的通信系统（100,300）同时并入并行从设备的编程（320,330,340,350） 使用I2C串行总线。 至少两个从设备在数据传输总线上并联耦合，并配置为使用通信协议通过串行数据线加载串行数据。 每个从设备包括可编程配置寄存器，其被配置为使用通信协议来编程以选择多个可选择的从设备配置中的一个。 可选择的从设备配置之一使得至少两个从设备并行加载串行数据，另一个可选择的从设备配置使得至少两个从设备一次一个地加载。
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公开(公告)号：US06636924B1
公开(公告)日：2003-10-21
申请号：US09641177
申请日：2000-08-17
申请人： Alma Anderson
发明人： Alma Anderson
IPC分类号： G06F1338
CPC分类号： G06F13/4022
摘要： A multiport device is configured to recognize each active segment on a bus, and to selectively propagate signals within the device depending upon whether the segment is active. Optimal signal propagation is achieved by invoking the control of the propagation of signals only after a first active-transition on the bus. Initial transitions are propagated unconditionally, to minimize propagation delay, and subsequent signal propagations are conditionally controlled, to avoid latch-up. A latch is associated with each port. The latch is set each time the port is actively driven by a device on that port. The latch is reset when all the devices are in the quiescent state, or when another port remains active after the currently active port becomes inactive. The state of each port's latch controls the propagation of internally generated signals to the port. If the latch is set, internally generated signals are not propagated to the port, thereby preventing latch-up. If the latch is not set, both internally generated signals and externally generated signals are propagated to the port, thereby minimizing propagation delays.
摘要翻译： 多端口设备被配置为识别总线上的每个活动段，并且根据段是否有效来选择性地传播设备内的信号。 通过仅在总线上的第一主动转换之后调用信号传播的控制来实现最佳信号传播。 无条件地传播初始转换，以最小化传播延迟，并有条件地控制随后的信号传播，以避免闩锁。 一个锁存器与每个端口相关联。 每次端口由该端口上的设备主动驱动时，锁存器被置位。 当所有设备处于静止状态时，或当当前活动端口变为非活动状态时，其他端口保持活动状态时，锁存器将复位。 每个端口的锁存器的状态控制内部生成的信号到端口的传播。 如果锁存器被置位，内部产生的信号不会传播到端口，从而防止闩锁。 如果锁存器未被置位，则内部产生的信号和外部产生的信号被传播到端口，从而最小化传播延迟。
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公开(公告)号：US07990081B2
公开(公告)日：2011-08-02
申请号：US12294001
申请日：2007-03-20
申请人： Manoj Chandran , Alma Anderson
发明人： Manoj Chandran , Alma Anderson
CPC分类号： H05B33/086 , H05B33/0818 , Y02B20/346
摘要： Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.
摘要翻译： 描述了实现和操作基于脉宽调制的LED调光控制器的方法和装置。 同步协议用于允许调光器操作的控制信息从外部时钟域传送到PWM调光控制时钟域，使得当更新控制信息时可防止视觉伪像。 控制信息可以通过I2C串行总线传输到LED调光控制器，并且在更新时钟域边界之间的控制信息之前，同步协议等待I2C STOP条件。 生成断言组调光控制信号的前沿和后沿，使得组调光控制信号的有效部分与各个LED脉冲宽度调制控制信号的有效部分重叠。 以这种方式，各个LED控制信号的脉冲宽度调制不被切断，或者通过组调光信号减小宽度。
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