公开(公告)号：US08436671B2

公开(公告)日：2013-05-07

申请号：US12859456

申请日：2010-08-19

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

IPC: H03L5/00

CPC classification number: H03K3/02 ,  H03K19/018521 ,  H03K19/018528

Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

Abstract translation: 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

公开(公告)号：US20120268196A1

公开(公告)日：2012-10-25

申请号：US13535034

申请日：2012-06-27

Applicant: Tien Chun YANG ,  Chih-Chang LIN ,  Ming-Chieh HUANG

Inventor： Tien Chun YANG ,  Chih-Chang LIN ,  Ming-Chieh HUANG

IPC: G05F1/10

CPC classification number: G11C5/145 ,  G11C11/4074

Abstract: A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.

Abstract translation: 提供了一种用于调节电荷泵的调节器。 调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。 第一电压与电荷泵的输出电压相关联。 第二电压与内部电源电压和参考电压Vref相关联。

公开(公告)号：US20120032731A1

公开(公告)日：2012-02-09

申请号：US12849503

申请日：2010-08-03

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Tien-Chun YANG ,  Yuwen SWEI

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Tien-Chun YANG ,  Yuwen SWEI

IPC: G05F3/02 ,  H01L25/00

CPC classification number: H02M3/07

Abstract: An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

Abstract translation: 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

公开(公告)号：US20120013374A1

公开(公告)日：2012-01-19

申请号：US12835130

申请日：2010-07-13

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Abstract translation: 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

公开(公告)号：US20110285445A1

公开(公告)日：2011-11-24

申请号：US12782064

申请日：2010-05-18

Applicant: Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03L5/00 ,  H03B5/30 ,  H02K33/00

CPC classification number: H03B5/30

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract translation: 一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

公开(公告)号：US20080127015A1

公开(公告)日：2008-05-29

申请号：US11590076

申请日：2006-10-30

Applicant: Bharat Chandramouli ,  Huan-Chih Tsai ,  Manish Pandey ,  Chih-Chang Lin ,  Madan M. Das

Inventor： Bharat Chandramouli ,  Huan-Chih Tsai ,  Manish Pandey ,  Chih-Chang Lin ,  Madan M. Das

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.

Abstract translation: 公开了用于验证低功率设计的功率规格的方法和系统。 该方法包括接收低功率设计的寄存器传送级（RTL）网表表示，接收用于描述低功率设计的功率需求的功率规格文件，并根据低功率设计的RTL网表表示验证功率规格文件 电源设计。 该方法还包括验证低功率设计的功率要求的完整性，兼容性和一致性。

公开(公告)号：US07266790B2

公开(公告)日：2007-09-04

申请号：US10656801

申请日：2003-09-04

Applicant: Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

Inventor： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Abstract translation: 一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。 这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

公开(公告)号：US07137084B1

公开(公告)日：2006-11-14

申请号：US10832771

申请日：2004-04-26

Applicant: Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

Inventor： Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.

Abstract translation: 用于对电路设计进行建模的方法包括合成电路设计以创建电路设计的第一门级表示。 该方法还包括分析电路设计的第二门级表示以学习架构信息，以及重新合成电路设计的第一门级表示，以从电路设计的第二门级表示中并入所学习的体系结构信息。 计算机可读存储介质上存储有计算机指令，其在由计算机执行时使计算机合成电路设计以创建电路设计的第一门级表示。 计算机指令还使得计算机分析电路设计的第二门级表示以学习架构信息，并重新合成电路设计的第一门级表示，以将来自第二门级表示的学习架构信息 电路设计。

公开(公告)号：US07057672B2

公开(公告)日：2006-06-06

申请号：US09823078

申请日：2001-03-29

Applicant: Bal S. Sandhu ,  Yanmei Tian ,  Chih-Chang Lin

Inventor： Bal S. Sandhu ,  Yanmei Tian ,  Chih-Chang Lin

IPC: H04N5/38 ,  H03F3/45

CPC classification number: G09G5/006 ,  G09G5/363 ,  G09G2330/12

Abstract: A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.

公开(公告)号：US20050146245A1

公开(公告)日：2005-07-07

申请号：US10745592

申请日：2003-12-29

Applicant: Chin-Wen Chou ,  Eddie Cheng ,  K. Wu ,  Chih-Chang Lin

Inventor： Chin-Wen Chou ,  Eddie Cheng ,  K. Wu ,  Chih-Chang Lin

IPC: H01L41/04 ,  H01L41/107 ,  H02M7/217 ,  H05B41/282

CPC classification number: H05B41/2828 ,  H01L41/044

Abstract: A ceramic transformer level driving circuit mainly aims to transform a low voltage signal to another low voltage signal through an amplified signal to drive a medium voltage system. It includes a control unit to generate a resonant frequency and output phase signal waveforms, a waveform transformation unit to provide phase signals and perform waveform phase transformation for the phase signal waveforms, and a medium voltage driving circuit which includes a floating level unit and a driving unit which receives a medium voltage electric input. The driving unit actuates opening and closing at different time to enable the floating level unit to output a voltage floating level thereby to drive a ceramic transformer to control the medium voltage system through a low voltage level.

Abstract translation: 陶瓷变压器电平驱动电路主要是通过放大信号将低电压信号转换为另一低电压信号，以驱动中压系统。 它包括产生谐振频率和输出相位信号波形的控制单元，提供相位信号并对相位信号波形执行波形相位变换的波形变换单元，以及包括浮置电平单元和驱动的中压驱动电路 接收中压电输入的单元。 驱动单元在不同时间启动打开和关闭，以使浮动水平单元能够输出电压浮动电平，从而驱动陶瓷变压器以通过低电压电平控制中压系统。