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11.发明授权公开(公告)号：US08174904B2
公开(公告)日：2012-05-08
申请号：US12898691
申请日：2010-10-05
Applicant: Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
Inventor： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G11C16/0475 , G11C16/04 , G11C16/3445 , G11C29/50 , G11C29/50004 , G11C29/52
Abstract: An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.
Abstract translation: 本发明的一个实施例提供一种包括多个位线，多个存储单元和一个设备的存储器阵列。 多个存储单元中的每一个具有第一节点，第二节点和第三节点，其中第三节点耦合到多个位线之一。 该设备将多个位线耦合在一起以形成多个存储器单元之一的公共节点。
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公开(公告)号：US08085016B2
公开(公告)日：2011-12-27
申请号：US12384442
申请日：2009-04-03
Applicant: Ching-Chung Lin
Inventor： Ching-Chung Lin
IPC: G05F1/00
CPC classification number: G06F1/3203 , G06F1/3265 , G06F1/3287 , Y02D10/153 , Y02D10/171 , Y02D50/20
Abstract: A power supply circuit includes a voltage output controller configured for outputting voltages, a standby controller configured for directing the voltage output controller to provide voltage to a load, and a microprocessor configured for controlling the standby controller according to a mode of the load. The voltage output controller is applied with a direct current voltage. When the load enters active mode from a powered off mode, the standby controller sends a control signal to the voltage output controller to output direct current voltage to the load and the microprocessor. When the load enters standby mode from the active mode, the microprocessor directs the standby controller to prevent the voltage output controller from outputting direct current voltage to the load and the microprocessor.
Abstract translation: 电源电路包括被配置为输出电压的电压输出控制器，被配置为用于引导电压输出控制器向负载提供电压的备用控制器，以及被配置为根据负载模式控制备用控制器的微处理器。 电压输出控制器采用直流电压。 当负载从电源关闭模式进入主动模式时，待机控制器向电压输出控制器发送控制信号，以将负载和微处理器的直流电压输出。 当负载从主动模式进入待机模式时，微处理器指示备用控制器，以防止电压输出控制器向负载和微处理器输出直流电压。
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公开(公告)号：US20090287946A1
公开(公告)日：2009-11-19
申请号：US12454453
申请日：2009-05-18
Applicant: Ching-Chung Lin
Inventor： Ching-Chung Lin
CPC classification number: H02J9/005 , G06F1/3203 , G06F1/3265 , Y02D10/153
Abstract: A power supply control circuit includes a standby control circuit, a microprocessor, and a power supply main circuit. The standby control circuit generates a pulse signal, outputs a first control signal, and sets the first control signal to an active state upon actuation of the switch member. The microprocessor outputs and sets a second control signal to first and second states upon first and second generations of the pulse signal, respectively. The standby control circuit maintains the first control signal at the active state when the second control signal is set to the first state, and sets the first control signal to an inactive state when the second control signal is set to the second state. The power supply main circuit outputs a power when the first control signal is set to the active state, and cuts off the power when the first control signal is set to the inactive state.
Abstract translation: 电源控制电路包括备用控制电路，微处理器和电源主电路。 备用控制电路产生脉冲信号，输出第一控制信号，并且在开关构件致动时将第一控制信号设置为活动状态。 微处理器分别在脉冲信号的第一代和第二代输出并将第二控制信号设置为第一和第二状态。 当第二控制信号被设置为第一状态时，备用控制电路将第一控制信号保持在激活状态，并且当第二控制信号被设置为第二状态时，将第一控制信号设置为无效状态。 当第一控制信号被设置为有效状态时，电源主电路输出电力，并且当第一控制信号被设置为非活动状态时，电源主电路输出电力。
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14.发明授权公开(公告)号：US07397717B2
公开(公告)日：2008-07-08
申请号：US11137503
申请日：2005-05-26
Applicant: Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
Inventor： Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
IPC: G11C7/10
CPC classification number: G11C7/1075 , G11C5/066
Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
Abstract translation: 串行外围闪存器件使用多个虚拟输入/输出端子，以便能够对具有较慢串行时钟速度的器件选择并行模式。 在并行模式下，通过多个虚拟输入/输出端子发送数据，以允许同时发送多个位，以较慢的串行时钟速度提高数据传输速率。
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15.发明授权公开(公告)号：US07002850B2
公开(公告)日：2006-02-21
申请号：US10886076
申请日：2004-07-06
Applicant: Ching-chung Lin , Nai-ping Kuo , Han-sung Chen
Inventor： Ching-chung Lin , Nai-ping Kuo , Han-sung Chen
IPC: G11C16/04
CPC classification number: G11C16/3468
Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the disclosed NROM erase system is also described.
Abstract translation: 公开了一种氮化物只读存储器（NROM）擦除系统。 NROM擦除系统包括至少一个存储器扇区，N个读出放大器和N个缓冲器。 根据感测放大器的数量，存储器扇区被分割成N个擦除重试单元。 一个缓冲器对应于一个擦除重试单元和一个读出放大器。 N个缓冲器用于指示在擦除操作的擦除处理之后它们相应的擦除重试单元是否被擦除。 如果其相应的擦除重试单元未被擦除，其中一个缓冲区将被设置。 在这种情况下，随后的擦除过程将开始擦除未擦除的擦除重试单元。 在以前的擦除过程中擦除的擦除重试单元不会受到后续擦除过程的影响。 还描述了使用所公开的NROM擦除系统的方法。
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Patent Agency Ranking
公开(公告)号：US5639065A
公开(公告)日：1997-06-17
申请号：US529731
申请日：1995-09-18
Applicant: Ching-Chung Lin
Inventor： Ching-Chung Lin
CPC classification number: B60S9/20
Abstract: A vehicle jack including a top table fixed to the bottom side of a motor vehicle, a control unit mounted on the top table, the control unit having a rotation control lever, a lifting control lever, and an extension control lever, a power unit, which includes a battery, a motor connected to the battery, an oil tank, a hydraulic oil loop, and a pump driven by the motor to pump hydraulic oil out of the oil tank into the hydraulic oil loop, a base table revolvably coupled to the top table, the base table having a driven gear fastened to the top table, a driving gear meshed with the driven gear and driven by the rotation control lever through a motor pump being coupled to the hydraulic oil loop, and three stands equiangularly pivoted to the base table, each stand having two opposite reciprocating parts reciprocated by hydraulic oil from the hydraulic oil loop through the control of the lifting control lever and extension control lever of the control unit.
Abstract translation: 一种车载千斤顶，包括固定在机动车辆底部的顶台，安装在顶台上的控制单元，具有旋转控制杆的控制单元，升降控制杆和延伸控制杆，动力单元， 其包括电池，连接到电池的电机，油箱，液压油回路和由电动机驱动的泵，以将液压油从油箱中泵出到液压油回路中;基座，可转动地联接到 顶台，底座具有紧固到顶台的从动齿轮，与从动齿轮啮合并由旋转控制杆通过联接到液压油回路的马达泵驱动的驱动齿轮，以及三个立方体等同地枢转到 基座台，每个支架具有两个相对的往复运动部件，通过液压油从液压油回路通过控制单元的提升控制杆和伸展控制杆的控制而往复运动。
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公开(公告)号：USD337996S
公开(公告)日：1993-08-03
申请号：US765868
申请日：1991-09-26
Applicant: Ching-Chung Lin
Designer： Ching-Chung Lin
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公开(公告)号：USD319817S
公开(公告)日：1991-09-10
申请号：US362297
申请日：1989-06-06
Applicant: Ching-Chung Lin
Designer： Ching-Chung Lin
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公开(公告)号：US08181052B2
公开(公告)日：2012-05-15
申请号：US12454453
申请日：2009-05-18
Applicant: Ching-Chung Lin
Inventor： Ching-Chung Lin
IPC: G06F1/32
CPC classification number: H02J9/005 , G06F1/3203 , G06F1/3265 , Y02D10/153
Abstract: A power supply control circuit includes a standby control circuit, a microprocessor, and a power supply main circuit. The standby control circuit generates a pulse signal, outputs a first control signal, and sets the first control signal to an active state upon actuation of the switch member. The microprocessor outputs and sets a second control signal to first and second states upon first and second generations of the pulse signal, respectively. The standby control circuit maintains the first control signal at the active state when the second control signal is set to the first state, and sets the first control signal to an inactive state when the second control signal is set to the second state. The power supply main circuit outputs a power when the first control signal is set to the active state, and cuts off the power when the first control signal is set to the inactive state.
Abstract translation: 电源控制电路包括备用控制电路，微处理器和电源主电路。 备用控制电路产生脉冲信号，输出第一控制信号，并且在开关构件致动时将第一控制信号设置为活动状态。 微处理器分别在脉冲信号的第一代和第二代输出并将第二控制信号设置为第一和第二状态。 当第二控制信号被设置为第一状态时，备用控制电路将第一控制信号保持在激活状态，并且当第二控制信号被设置为第二状态时，将第一控制信号设置为无效状态。 当第一控制信号被设置为有效状态时，电源主电路输出电力，并且当第一控制信号被设置为非活动状态时，电源主电路输出电力。
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公开(公告)号：US07830723B2
公开(公告)日：2010-11-09
申请号：US12423013
申请日：2009-04-14
Applicant: Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
Inventor： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G11C16/0475 , G11C16/04 , G11C16/3445 , G11C29/50 , G11C29/50004 , G11C29/52
Abstract: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.
Abstract translation: NROM存储器件包括存储器单元阵列和第一和第二位线。 第一和第二位线耦合到存储器单元的相对侧。 在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。 还公开了可以容易地基于存储器单元的阈值电压分布来筛选边际存储器单元的方法。
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