公开(公告)号：US06511870B2

公开(公告)日：2003-01-28

申请号：US09850058

申请日：2001-05-08

Applicant: Chih-Chiang Chen ,  Jiun-Jye Chang ,  Ching-Sang Chuang

Inventor： Chih-Chiang Chen ,  Jiun-Jye Chang ,  Ching-Sang Chuang

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a polysilicon thin film transistor with a self-aligned lightly doped drain (LDD) is described. At first a polysilicon-island region and a gate insulating layer are subsequently formed on a glass substrate performed by a pre-treatment. Then a metal layer and a cap layer are subsequently formed on the gate insulating layer. The cap layer and the metal layer are defined to form a gate. A heavily doped region is formed in the polysilicon island region with serving the gate as a mask. An activation step is performed on the heavily doped region and a sidewall of the metal layer. The cap layer above the metal layer and the sidewall of the metal layer performed by the activation step are removed. A lightly doped region is formed in the polysilicon-island region with serving the remaining metal layer.

公开(公告)号：US08597968B2

公开(公告)日：2013-12-03

申请号：US13353328

申请日：2012-01-19

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

Abstract translation: 提供有源器件阵列衬底。 首先，提供具有显示区域和感测区域的基板。 然后，在基板的显示区域上设置第一图案化导体层。 栅极绝缘体设置在基板上。 图案化半导体层，第二图案化导体层和图案化感光介电层设置在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二 图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。 然后在衬底上设置钝化层。 之后，在钝化层上设置包括像素电极和上部电极的第三图案化导体层。

公开(公告)号：US08148185B2

公开(公告)日：2012-04-03

申请号：US12559506

申请日：2009-09-15

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.

Abstract translation: 提供一种用于制造有源器件阵列衬底的方法。 首先，提供具有显示区域和感测区域的基板。 然后，在基板的显示区域上形成第一图案化导体层。 在基板上形成栅极绝缘体。 图案化的半导体层，第二图案化导体层和图案化的光敏介电层形成在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二 图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。 然后在衬底上形成钝化层。 之后，在钝化层上形成包括像素电极和上电极的第三图案化导体层。

公开(公告)号：US20100112737A1

公开(公告)日：2010-05-06

申请号：US12416934

申请日：2009-04-02

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

IPC: H01L21/3115

CPC classification number: G02F1/133555 ,  G02F2001/136231

Abstract: A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced.

Abstract translation: 本发明的形成方法包括形成第一图案化导电层，其包括在基板上堆叠在一起的透明导电层和金属层，其中第一图案化导电层用作栅极线，栅电极，共同线和预定透明 像素电极结构; 以及在所述衬底上形成第二图案化导电层。 第二图案化导电层包括数据线和反射像素电极，并且直接连接到诸如源极区/漏极区的掺杂区。 根据本发明的形成方法，可以通过五个掩模工艺形成半透射型液晶显示装置的像素结构。 因此，有效地简化了半透射型液晶显示装置的制造工艺，从而提高了产品成品率，降低了成本。

公开(公告)号：US20050250050A1

公开(公告)日：2005-11-10

申请号：US10650977

申请日：2003-08-29

Applicant: Chih-Chiang Chen ,  Ching-Sang Chuang ,  Jiun-Jye Chang

Inventor： Chih-Chiang Chen ,  Ching-Sang Chuang ,  Jiun-Jye Chang

IPC: H01L21/027 ,  G03F7/00 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A method of forming a top gate thin film transistor (TFT). By performing photolithography using a first reticle, a photoresist layer having a thick photoresist layer portion and a thin photoresist layer portion is formed on a silicon layer in an active area. Thus, a channel layer and source/drain regions in a silicon island are defined by the same patterning process. In addition, a gate and an LDD region in the silicon island are defined by photolithography using a second reticle and a backside exposure process. Accordingly, the top gate TFT fabrication process of the present invention requires only two reticles, and thereby reduces costs.

Abstract translation: 一种形成顶栅极薄膜晶体管（TFT）的方法。 通过使用第一掩模版进行光刻，在活性区域的硅层上形成具有厚的光致抗蚀剂层部分和光致抗蚀剂层部分的光致抗蚀剂层。 因此，通过相同的图案化工艺限定硅岛中的沟道层和源/漏区。 此外，硅岛中的栅极和LDD区域通过使用第二掩模版和背面曝光工艺的光刻来定义。 因此，本发明的顶栅TFT制造方法仅需要两个掩模版，从而降低成本。