公开(公告)号：US20160211378A1

公开(公告)日：2016-07-21

申请号：US15083251

申请日：2016-03-28

Applicant: Kook-Tae KIM ,  Young-Tak KIM ,  Ho-Sung SON ,  Seok-Jun WON ,  Ji-Hye YI ,  Chul-Woong LEE

Inventor： Kook-Tae KIM ,  Young-Tak KIM ,  Ho-Sung SON ,  Seok-Jun WON ,  Ji-Hye YI ,  Chul-Woong LEE

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Abstract translation: 提供半导体装置及其制造方法以及包括半导体装置的电子装置。 半导体器件包括形成在衬底上并包括沟槽的层间绝缘层，形成在沟槽中的栅电极，形成在栅电极的侧壁上以形成L形的第一栅极间隔件，形成在第二栅极间隔 所述第一栅极间隔物具有L形并且具有低于氮化硅的介电常数的介电常数，以及形成在所述第二栅极间隔物上的第三间隔物。

公开(公告)号：US09214530B2

公开(公告)日：2015-12-15

申请号：US14033639

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US06760942B2

公开(公告)日：2004-07-13

申请号：US09853613

申请日：2001-05-14

Applicant: Chul Woong Lee ,  Jae Cheon Lee ,  Min Kyu Hwang

Inventor： Chul Woong Lee ,  Jae Cheon Lee ,  Min Kyu Hwang

IPC: D06F3302

CPC classification number: D06F33/02 ,  D06F35/006 ,  D06F2202/10 ,  D06F2204/065

Abstract: An apparatus and method for determining a washing pattern of a direct drive inverter-type washing machine. The apparatus comprises a voltage converter for inputting an external alternating current (AC) voltage and rectifying and smoothing the inputted AC voltage to convert it into a drive voltage necessary to a washing mode of a washing machine, a switch for performing a switching operation in response to a motor drive control signal to transfer the drive voltage from the voltage converter to a motor so as to rotate or stop a washing tub, a voltage variation sensing device for measuring a voltage variation when the motor rotates in response to the drive voltage transferred from the switch and outputting the measured result as a voltage variation sense signal, and a microcomputer for driving the motor in a laundry amount sensing pattern at the time that laundry is put into the washing tub, judging the amount of the laundry and the amount of water supply depending on the laundry amount, judging the type of a material of the laundry in response to the voltage variation sense signal at the time that wash water is supplied to the tub, producing an optimum washing pattern appropriate to the amount and material type of the laundry within the washing tub and generating the motor drive control signal to drive the motor in the produced optimum washing pattern.

Abstract translation: 一种用于确定直接驱动逆变式洗衣机的洗涤模式的装置和方法。 该装置包括用于输入外部交流（AC）电压并整流和平滑输入的AC电压以将其转换成洗衣机的洗涤模式所需的驱动电压的电压转换器，用于响应于执行开关操作的开关 电动机驱动控制信号，用于将驱动电压从电压转换器传递到电动机，以便旋转或停止洗涤桶;电压变化检测装置，用于测量电动机响应于从 开关并将测量结果作为电压变化检测信号输出;以及微型计算机，用于在衣物放入洗涤桶中时以衣物量检测图案驱动电动机，判断衣物量和水量 根据衣物量进行供给，根据当时的电压变化检测信号判断衣物的种类 将洗涤水供应到桶中，产生适合洗涤桶内的衣物的量和材料类型的最佳洗涤图案，并产生电动机驱动控制信号，以产生最佳洗涤图案驱动电动机。

公开(公告)号：US06369538B1

公开(公告)日：2002-04-09

申请号：US09612915

申请日：2000-07-10

Applicant: Sang Chul Youn ,  Joo Hwan Lee ,  Chul Woong Lee ,  In Hwan Ra

Inventor： Sang Chul Youn ,  Joo Hwan Lee ,  Chul Woong Lee ,  In Hwan Ra

IPC: H02K2300

CPC classification number: D06F33/02 ,  D06F37/40 ,  D06F2204/065 ,  D06F2212/02 ,  H02P3/18

Abstract: This invention relates to a method for braking a washing machine comprising the steps of: determining whether or not a motor is braking; transmitting a PWM (Pulse Width Modulation) control signal by setting up the initial phase and the duty ratio according to the voltage flows in the system when an operation mode determined by the previous step as a braking mode; comparing a capacity and a variance of the detected voltage with a reference voltage predetermined during the previous step; and controlling a motor driver by re-establishing the control phase and the duty ratio are re-established until the motor is stopped when the comparison result of the previous step indicates that the capacity and the variance of the voltage are lower than the predetermined reference level.

Abstract translation: 本发明涉及一种用于制动洗衣机的方法，包括以下步骤：确定电动机是否制动; 当由前一步骤确定的操作模式作为制动模式时，根据系统中的电压流动设置初始相位和占空比来发送PWM（脉宽调制）控制信号; 将检测到的电压的容量和方差与在前一步骤中预定的参考电压进行比较; 并且当前一步骤的比较结果指示电压的容量和方差低于预定参考电平时，通过重新建立控制相位和占空比来重新建立电动机驱动器直到电动机停止为止 。

公开(公告)号：US09537009B2

公开(公告)日：2017-01-03

申请号：US14955289

申请日：2015-12-01

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US09520497B2

公开(公告)日：2016-12-13

申请号：US14951932

申请日：2015-11-25

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20160087101A1

公开(公告)日：2016-03-24

申请号：US14955289

申请日：2015-12-01

Applicant: Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US09257520B2

公开(公告)日：2016-02-09

申请号：US14680349

申请日：2015-04-07

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US09129952B2

公开(公告)日：2015-09-08

申请号：US14033718

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US09024385B2

公开(公告)日：2015-05-05

申请号：US14033718

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.