公开(公告)号：US20160148930A1

公开(公告)日：2016-05-26

申请号：US15009276

申请日：2016-01-28

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20150214329A1

公开(公告)日：2015-07-30

申请号：US14680349

申请日：2015-04-07

Applicant: Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US20140370699A1

公开(公告)日：2014-12-18

申请号：US14145188

申请日：2013-12-31

Applicant: Ju-Youn Kim ,  Chul-Woong Lee ,  Tae-Sun Kim ,  Sang-Duk Park ,  Bum-Joon Youn ,  Tae-Won Ha

Inventor： Ju-Youn Kim ,  Chul-Woong Lee ,  Tae-Sun Kim ,  Sang-Duk Park ,  Bum-Joon Youn ,  Tae-Won Ha

IPC: H01L21/308 ,  H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench and a second trench, forming a first conductive layer along sidewall surfaces and bottom surface of the first trench and forming a second conductive layer along sidewall surfaces and bottom surface of the second trench, forming a mask pattern on the second conductive layer, the mask pattern filling the second trench and being a bottom anti-reflective coating (BARC), and removing the first conductive layer using the mask pattern.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间绝缘层，所述层间绝缘层包括第一沟槽和第二沟槽，沿着所述第一沟槽的侧壁表面和底表面形成第一导电层，并形成第二导电 层，沿着第二沟槽的侧壁表面和底表面，在第二导电层上形成掩模图案，掩模图案填充第二沟槽并且是底部抗反射涂层（BARC），并且使用掩模去除第一导电层 模式。

公开(公告)号：US20140141589A1

公开(公告)日：2014-05-22

申请号：US14033639

申请日：2013-09-23

Applicant: Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20160079424A1

公开(公告)日：2016-03-17

申请号：US14951932

申请日：2015-11-25

Applicant: Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US07169879B2

公开(公告)日：2007-01-30

申请号：US11016293

申请日：2004-12-17

Applicant: Tae-Ho Yoon ,  Chul Woong Lee ,  Sang Min Kwak

Inventor： Tae-Ho Yoon ,  Chul Woong Lee ,  Sang Min Kwak

IPC: C08C73/00

CPC classification number: C08G73/0246 ,  C07F9/5325 ,  C07F9/5537

Abstract: The present invention relates to bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds and synthesis thereof, more particularly to novel bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds having both a perfluorinated benzene substituent and a phosphine oxide moiety. Compounds of the invention can be useful as a monomer for preparing polyimides having a low dielectric constant and a superior adhesion while maintaining the superior thermal and mechanical properties of polyimides themselves, and their synthesis thereof.

Abstract translation: 本发明涉及双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物及其合成，更具体地涉及新的双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物，其具有 全氟化苯取代基和氧化膦部分。 本发明的化合物可用作制备具有低介电常数和优异粘附性的聚酰亚胺的单体，同时保持聚酰亚胺本身的优异的热和机械性能及其合成。

公开(公告)号：US06445879B1

公开(公告)日：2002-09-03

申请号：US09612918

申请日：2000-07-10

Applicant: Sang Chul Youn ,  Joo Hwan Lee ,  Chul Woong Lee ,  In Hwan Ra ,  Beom Seok Ko

Inventor： Sang Chul Youn ,  Joo Hwan Lee ,  Chul Woong Lee ,  In Hwan Ra ,  Beom Seok Ko

IPC: H02P517

CPC classification number: H02P6/24 ,  D06F37/304 ,  Y02B40/52 ,  Y10S388/906

Abstract: A method for braking a washing machine in accordance with the present invention comprising the steps of: setting up an initial data of a duty ratio corresponding to a detected speed and a rotating position; discharging a voltage of the capacitor filter during a duty-on cycle according to the duty ratio set up in the preceding step; and charging a voltage to the capacitor filter during duty-off cycle when the duty-on cycle of the preceding step is finished. As described above, the dynamic braking resistor is not used in the method for braking the washing machine according to the present invention so that the size and the production cost are reduced.

Abstract translation: 一种根据本发明的制造洗衣机的方法，包括以下步骤：建立与检测速度和旋转位置相对应的占空比的初始数据; 根据上述步骤中设定的占空比，在占空比循环期间放电电容滤波器的电压; 并且当上一步骤的占空比循环完成时，在占空比循环期间向电容器滤波器充电。 如上所述，在根据本发明的洗衣机的制动方法中不使用动态制动电阻器，从而减小了尺寸和生产成本。

公开(公告)号：US09397216B2

公开(公告)日：2016-07-19

申请号：US14938172

申请日：2015-11-11

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20160064565A1

公开(公告)日：2016-03-03

申请号：US14938172

申请日：2015-11-11

Applicant: Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

Inventor： Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20140138745A1

公开(公告)日：2014-05-22

申请号：US14033718

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。