Abstract:
A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.
Abstract:
A method and a motherboard for automatically determining the memory type. By applying the characteristics of different operational voltages for various dynamic random access memory modules, a software program is used to drive a control signal and to automatically adjust the control voltage of the dynamic random access memory. An automatic detection of the types of the dynamic random access memory is obtained. The objectives of protecting the dynamic random access memory and to allow the dynamic random access memory to operate normally can thus be achieved. The invention not only provides the detection mechanism for accessing the dynamic random access memory during the initial activation of the computer system, but also determines the voltages required by the memory module for the computer system to enter various power saving modes.
Abstract:
A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.
Abstract:
A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.