公开(公告)号：US5894065A

公开(公告)日：1999-04-13

申请号：US802619

申请日：1997-02-19

Applicant: Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

Inventor： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

公开(公告)号：US20050064654A1

公开(公告)日：2005-03-24

申请号：US10964049

申请日：2004-10-12

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Cereda

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Cereda

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

Abstract translation: 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介电电荷俘获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。

公开(公告)号：US6063663A

公开(公告)日：2000-05-16

申请号：US139909

申请日：1998-08-26

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.

Abstract translation: 提供了一种在集成在半导体上的电路中制造P沟道天然MOS晶体管的方法，该半导体还包括浮置型非易失性存储单元的矩阵，其中两个多晶硅层具有夹在两个多晶硅之间的多晶硅间介电层 水平。 该方法具有以下步骤：（1）屏蔽和定义离散集成器件的有源区; （2）使用Poly1掩模掩蔽和限定第一多晶硅层; 和（3）使用矩阵掩模掩蔽和限定中间介电层。 天生晶体管的天生阈值通道的长度通过矩阵掩模定义，并通过蚀刻掉多余介电层。 掩蔽和限定第二多晶硅级别的后续步骤提供了使用Poly2掩模，该Poly2掩模以比先前掩模更大的宽度延伸晶体管的有源区，以便通过随后的蚀刻使两个多晶硅层重叠 在通道区域上自对准。