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1.发明授权
公开(公告)号：US5894065A
公开(公告)日：1999-04-13
申请号：US802619
申请日：1997-02-19
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.
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2.发明授权Method for improving the intermediate dielectric profile, particularly for non-volatile memories 失效用于改善中间介质轮廓的方法，特别是用于非易失性存储器
公开(公告)号：US6104058A
公开(公告)日：2000-08-15
申请号：US898155
申请日：1997-07-22
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.
摘要翻译： 一种用于改善中间介质轮廓的方法，特别是用于由多个单元构成的非易失性存储器，包括以下步骤：在衬底上形成场氧化物区域和漏极活性区域区域; 在场氧化物区域上形成字线; 沉积氧化物以形成与字线相邻的氧化物翼; 通过掩蔽来源区域和漏极有源区域区域，保持在抗蚀剂覆盖的存储器内部的一个存储单元与另一个存储单元分离的场氧化物区域; 并且去除源区域中的场氧化物并从字线的两侧去除氧化物翼。
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3.发明授权Process for manufacturing an integrated circuit comprising an array of memory cells 失效一种用于制造包括存储单元阵列的集成电路的方法公开(公告)号：US06353243B1
公开(公告)日：2002-03-05
申请号：US09356080
申请日：1999-07-16
IPC分类号： H01L2348
CPC分类号： H01L27/11526 , H01L23/5283 , H01L27/105 , H01L27/115 , H01L27/11543 , H01L2924/0002 , H01L2924/00
摘要： A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2).
摘要翻译： 一种用于制造集成电路的方法，该集成电路包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电互连的互连线（100）的第二层导电材料（11）的第二层（17），所述第二层导电材料（11） 提供通过第一掩模（MASK1）选择性地蚀刻存储单元阵列区域外的第一和第二导电材料层（9,11），并且所述第一条带（22）限定第二条带 导电材料（11），绝缘材料层（10）和第一层导电材料（9）通过第二掩模（MASK2）在存储单元阵列区域内。
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公开(公告)号：US5663080A
公开(公告)日：1997-09-02
申请号：US524080
申请日：1995-09-06
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L21/8238 , H01L21/8247 , H01L21/265
CPC分类号： H01L27/11526 , H01L21/76216 , H01L21/76218 , H01L21/823878 , H01L27/11546
摘要： A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.
摘要翻译： 一种用于制造集成电路的方法，包括以下步骤：选择性地增加部分地具有给定类型导电性的衬底内的绝缘材料的场绝缘区域; 在衬底上沉积多晶硅层; 通过掩模成形多晶硅层; 并且使用成形掩模通过场绝缘区域选择性地注入与衬底相同的导电类型的离子。 注入的离子穿透衬底并在场绝缘区域下方形成通道阻挡区域。
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5.发明授权Process for manufacturing an integrated circuit comprising an array of memory cells 失效一种用于制造包括存储单元阵列的集成电路的方法
公开(公告)号：US5976933A
公开(公告)日：1999-11-02
申请号：US897799
申请日：1997-07-21
IPC分类号： H01L21/8247 , H01L23/528 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11526 , H01L23/5283 , H01L27/115 , H01L27/11543 , H01L27/105 , H01L2924/0002
摘要： A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.
摘要翻译： 一种用于制造集成电路的方法，该集成电路包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电互连的互连线（100）的第二导电材料层（11）的第一层（17），所述第一条带（22）和 第二导电材料层（11）的第二条带（17）在其边界区域的各自端部自动连接。
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公开(公告)号：US5696399A
公开(公告)日：1997-12-09
申请号：US475555
申请日：1995-06-07
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L21/8238 , H01L21/8247 , H01L29/76
CPC分类号： H01L27/11526 , H01L21/76216 , H01L21/76218 , H01L21/823878 , H01L27/11546
摘要： A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.
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7.发明授权Method of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistors 失效制造具有高击穿电压的MOS晶体管的集成电路的方法，以及精密电阻器
公开(公告)号：US6027965A
公开(公告)日：2000-02-22
申请号：US67126
申请日：1998-04-27
IPC分类号： H01L27/04 , H01L21/02 , H01L21/329 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/8605
CPC分类号： H01L28/20 , H01L21/8234 , H01L27/0629 , H01L29/66166 , H01L29/8605
摘要： The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further includes low-dose ionic implantation through the implantation mask to form pairs of regions at the sides of the gate strips and resistive regions through the openings, the formation of an insulating layer on the entire structure thus produced, and anisotropic etching of the insulating layer so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask, but leaving a residue of insulating material along the edges of the gate strips. To compensate for the removal of a surface layer from the resistive regions due to the anisotropic etching, a second low-dose implantation is carried out without masking of the substrate, with a dose and an energy such as to produce a predetermined resistivity for the resistive regions without altering the resistivities of the source and drain regions of the MOS transistors.
摘要翻译： 所描述的方法提供了形成多晶硅的注入掩模，其包括用于提供MOS晶体管的栅电极和限定用于形成电阻器的开口的部分的条。 该方法还包括通过注入掩模的低剂量离子注入，以通过开口在栅极条和电阻区的侧面上形成一对区域，在由此产生的整个结构上形成绝缘层，以及各向异性蚀刻 绝缘层以露出未被多晶硅掩模覆盖的衬底的区域，但沿栅极条的边缘留下绝缘材料残留物。 为了补偿由于各向异性蚀刻而从电阻区域去除表面层，进行第二次低剂量注入，而不用衬底掩蔽，具有剂量和能量，以产生用于电阻的预定电阻率 区，而不改变MOS晶体管的源区和漏区的电阻率。
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8.发明授权Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits 失效在集成电子电路中自动对准导电材料的重叠线的方法公开(公告)号：US06350671B1
公开(公告)日：2002-02-26
申请号：US09579778
申请日：2000-05-26
IPC分类号： H01L214263
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76885 , H01L2924/3011
摘要： A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.
摘要翻译： 提出了一种在集成在半导体衬底上的电路中自动对准导电材料线的方法。 该方法包括形成从基板表面突出并且彼此对准的若干区域，并且在突出区域之间的间隙中形成填充层。 将填充层平坦化以暴露区域，并且去除部分区域以在区域的位置处形成孔。 接下来，在孔中形成绝缘层。 选择性地去除绝缘层以沿着所述孔的边缘形成间隔物，并且至少一个导电层沉积在暴露的表面上。 之后，进行用掩模进行光刻的步骤，蚀刻导电层以限定线并将它们准直到下面的区域。
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9.发明授权Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories 有权用于制造非易失性存储器的工艺的原生MOS P沟道晶体管的制造方法
公开(公告)号：US6063663A
公开(公告)日：2000-05-16
申请号：US139909
申请日：1998-08-26
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11541 , H01L27/11543
摘要： A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.
摘要翻译： 提供了一种在集成在半导体上的电路中制造P沟道天然MOS晶体管的方法，该半导体还包括浮置型非易失性存储单元的矩阵，其中两个多晶硅层具有夹在两个多晶硅之间的多晶硅间介电层 水平。 该方法具有以下步骤：（1）屏蔽和定义离散集成器件的有源区; （2）使用Poly1掩模掩蔽和限定第一多晶硅层; 和（3）使用矩阵掩模掩蔽和限定中间介电层。 天生晶体管的天生阈值通道的长度通过矩阵掩模定义，并通过蚀刻掉多余介电层。 掩蔽和限定第二多晶硅级别的后续步骤提供了使用Poly2掩模，该Poly2掩模以比先前掩模更大的宽度延伸晶体管的有源区，以便通过随后的蚀刻使两个多晶硅层重叠 在通道区域上自对准。
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公开(公告)号：US07115472B2
公开(公告)日：2006-10-03
申请号：US10964049
申请日：2004-10-12
IPC分类号： H01L21/8242
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923
摘要： A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.
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