公开(公告)号：US4792925A

公开(公告)日：1988-12-20

申请号：US783650

申请日：1985-10-03

申请人： Giuseppe Corda ,  Andrea Ravaglia

发明人： Giuseppe Corda ,  Andrea Ravaglia

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： H01L27/115 ,  G11C16/0416

摘要： The invention provides an EPROM memory matrix and a method of writing to an EPROM memory matrix. Two pluralities of parallel source lines alternate with parallel drain lines while floating gate areas span the source and drain lines and parallel control gate lines are arranged perpendicularly to the source and drain lines and superimposed on and self-aligned with the floating gate areas. During the writing operation, the gate and drain lines corresponding to a selected cell are connected to a positive voltage source and the source line corresponding to the selected cell is connected to earth together with all the other source lines of the same plurality while all the source lines of the other plurality are left at a potential intermediate between said positive voltage and earth.

摘要翻译： 本发明提供一种EPROM存储器矩阵和写入EPROM存储器矩阵的方法。 两条并行的源极线与并行的漏极线交替，而浮动栅极区域跨越源极和漏极线，并行的控制栅极线垂直于源极和漏极线布置并且叠加在浮动栅极区域上并与其自对准。 在写入操作期间，对应于所选择的单元的栅极和漏极线连接到正电压源，并且与所选择的单元相对应的源极线与所有其他源极线连接到地球，同时所有源极 其他多个的线路保持在所述正电压和地之间的电位中间。

公开(公告)号：US4310571A

公开(公告)日：1982-01-12

申请号：US34204

申请日：1979-04-27

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

IPC分类号： H01C17/24 ,  H01L21/02 ,  H01L21/033 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01C17/06

CPC分类号： H01L28/20 ,  H01L21/033 ,  Y10T29/49082 ,  Y10T29/49099

摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。

公开(公告)号：US4868136A

公开(公告)日：1989-09-19

申请号：US178822

申请日：1988-03-24

申请人： Andrea Ravaglia

发明人： Andrea Ravaglia

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76221 ,  H01L21/308 ,  H01L21/32 ,  Y10S438/975

摘要： Two thin wedges of oxide extending along and from the boundaries of the field oxide layer without solution of continuity inside the substrate for a depth such as to separate dielectrically the region of silicon, present underneath the field oxide layer, having a doping level higher than the doping level of the bulk of the substrate and the regions of oppositely doped silicon in a MOS device allow obtaining simultaneously a high threshold voltage of the parasitic transistor, a high junction breakdown voltage and an excellent immunity to "Reach-through" between the depletion regions of uncorrelated junctions together with a reduced capacitance of the junctions and an improved geometry. Such wedges of oxide are obtained by means of deep anisotropic etch of silicon through a suitably exposed area, for example by means of an overetch of the nitride used for growing the thick oxide layer according to the known technique and by the subsequent filling of the deep etch with thermally grown silicon oxide.

摘要翻译： 两个薄的氧化物沿着场氧化物层的边界延伸并且没有在衬底内部的连续性的溶液的深度，以便介电地存在位于场氧化物层下面的硅的区域，该区域的掺杂水平高于 衬底的大部分的掺杂水平和MOS器件中相反掺杂的硅的区域允许同时获得寄生晶体管的高阈值电压，高结击穿电压和对耗尽区域之间的“到达”的优异抗扰性 不相关的连接点以及连接点的电容减小以及改进的几何形状。 氧化物的这种楔形是通过在适当暴露的区域的硅进行深度各向异性蚀刻而获得的，例如通过用于根据已知技术生长厚氧化物层的氮化物的过蚀刻以及随后的深度填充 用热生长的氧化硅蚀刻。

公开(公告)号：US5894065A

公开(公告)日：1999-04-13

申请号：US802619

申请日：1997-02-19

申请人： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

发明人： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

公开(公告)号：US4622737A

公开(公告)日：1986-11-18

申请号：US764985

申请日：1985-08-12

申请人： Andrea Ravaglia

发明人： Andrea Ravaglia

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7883 ,  H01L27/115

摘要： On the doped area of a monocrystalline silicon substrate is grown a thick oxide layer a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicon on which is then grown thin oxide; polycrystalline silicon layers separated by an oxide layer are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one of said polycrystalline silicon layers is separated from the underlying doped area of the substrate, which constitutes the drain, by a very small thin oxide area which adjoins an extended area of thick oxide. The electrical capacitance between the floating gate and the drain is thus reduced with resulting smaller dimensions of the cell for given performance.

摘要翻译： 在单晶硅衬底的掺杂区域上生长厚度的氧化物层，其侧面在预定区域内进行蚀刻和脱落，直到其露出硅然后生长为薄氧化物的边缘; 然后沉积由氧化物层分离的多晶硅层以产生非易失性存储单元，其中由一个所述多晶硅层组成的浮动栅极与构成漏极的衬底的下面的掺杂区域分开非常小的 邻接厚氧化物的延伸区域的薄氧化物区域。 因此浮动栅极和漏极之间的电容减小，从而导致用于给定性能的电池的较小尺寸。

公开(公告)号：US4315239A

公开(公告)日：1982-02-09

申请号：US177595

申请日：1980-08-13

申请人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

发明人： Vincenzo Daniele ,  Giuseppe Corda ,  Andrea Ravaglia ,  Giuseppe Ferla

IPC分类号： H01C17/24 ,  H01L21/02 ,  H01L21/033 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01C1/02

CPC分类号： H01L28/20 ,  H01L21/033 ,  Y10T29/49082 ,  Y10T29/49099

摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.

摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。

公开(公告)号：US6104058A

公开(公告)日：2000-08-15

申请号：US898155

申请日：1997-07-22

申请人： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

发明人： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

摘要翻译： 一种用于改善中间介质轮廓的方法，特别是用于由多个单元构成的非易失性存储器，包括以下步骤：在衬底上形成场氧化物区域和漏极活性区域区域; 在场氧化物区域上形成字线; 沉积氧化物以形成与字线相邻的氧化物翼; 通过掩蔽来源区域和漏极有源区域区域，保持在抗蚀剂覆盖的存储器内部的一个存储单元与另一个存储单元分离的场氧化物区域; 并且去除源区域中的场氧化物并从字线的两侧去除氧化物翼。

公开(公告)号：US5663080A

公开(公告)日：1997-09-02

申请号：US524080

申请日：1995-09-06

申请人： Manlio Sergio Cereda ,  Giancarlo Ginami ,  Enrico Laurin ,  Andrea Ravaglia

发明人： Manlio Sergio Cereda ,  Giancarlo Ginami ,  Enrico Laurin ,  Andrea Ravaglia

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/265

CPC分类号： H01L27/11526 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/823878 ,  H01L27/11546

摘要： A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

摘要翻译： 一种用于制造集成电路的方法，包括以下步骤：选择性地增加部分地具有给定类型导电性的衬底内的绝缘材料的场绝缘区域; 在衬底上沉积多晶硅层; 通过掩模成形多晶硅层; 并且使用成形掩模通过场绝缘区域选择性地注入与衬底相同的导电类型的离子。 注入的离子穿透衬底并在场绝缘区域下方形成通道阻挡区域。