公开(公告)号：US06826071B2

公开(公告)日：2004-11-30

申请号：US10098262

申请日：2002-03-15

申请人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

发明人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

IPC分类号： G11C1700

CPC分类号： G11C17/18

摘要： A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory. The method includes the steps of: connecting the antifuse in series with a node; providing current to the node through a parallel combination of a first transistor and a second transistor that is sufficient to charge the node from a first voltage to a second voltage; and detecting whether the voltage at the node charges to the second voltage or remains at the first voltage to indicate that the antifuse is programmed properly; outputting first and second signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is programmed properly.

摘要翻译： 验证半导体存储器中未编程的反熔丝是否泄漏的方法。 该方法包括以下步骤：将反熔丝与节点串联连接; 向节点提供电流，电流足以使节点从第一电压到第二电压充电; 检测节点处的电压是否充电到第二电压，或者保持在第一电压以指示反熔丝泄漏; 输出指示检测结果的信号; 并且检测节点处的电压保持在第一电压，表示反熔丝泄漏。 在另一个实施例中，验证在半导体存储器中是否正确地编程了反熔丝的方法。 该方法包括以下步骤：将反熔丝与节点串联连接; 通过第一晶体管和第二晶体管的并联组合向节点提供电流，其足以将节点从第一电压充电到第二电压; 并且检测节点处的电压是否充电到第二电压或者保持在第一电压以指示反熔丝被正确编程; 输出表示检测结果的第一和第二信号; 并且检测节点处的电压保持在第一电压，表示反熔丝被正确编程。

公开(公告)号：US06590407B2

公开(公告)日：2003-07-08

申请号：US10222113

申请日：2002-08-16

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06452846B1

公开(公告)日：2002-09-17

申请号：US09733434

申请日：2000-12-08

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06418071B2

公开(公告)日：2002-07-09

申请号：US09735329

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06188622B1

公开(公告)日：2001-02-13

申请号：US09483264

申请日：2000-01-13

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C2900

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6052322A

公开(公告)日：2000-04-18

申请号：US363003

申请日：1999-07-28

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6026040A

公开(公告)日：2000-02-15

申请号：US259220

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US5877993A

公开(公告)日：1999-03-02

申请号：US855555

申请日：1997-05-13

申请人： Kurt D. Biegel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Biegel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06903991B2

公开(公告)日：2005-06-07

申请号：US10178605

申请日：2002-06-24

申请人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

发明人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

IPC分类号： G01F1/66 ,  G01F1/684 ,  G01F1/696 ,  G01F1/86 ,  G01F5/00 ,  G01F25/00 ,  G11C17/00 ,  G11C17/16 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

摘要翻译： 提供用于编程反熔丝元件的电路，其允许同时对一个组中的所有反熔丝元件进行编程，从而提高可以对反熔丝元件进行编程的速度。 在一个实施例中，反馈电路与每个反熔丝元件相关联，以便在程序设计之后停止通过反熔丝元件的电流流动。 在另一个实施例中，提供电路用于为每个用于编程的反熔丝元件产生单独的编程脉冲。

公开(公告)号：US06646459B2

公开(公告)日：2003-11-11

申请号：US09813130

申请日：2001-03-19

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。