公开(公告)号：US08523570B2

公开(公告)日：2013-09-03

申请号：US12784797

申请日：2010-05-21

申请人： Satya P. Mallick ,  Kevin Barnes ,  Margaret Rose Ciafardini Kirkland ,  Kristine Anna Dougherty ,  Deepu John ,  David Kriegman ,  Vipanj B. Patel

发明人： Satya P. Mallick ,  Kevin Barnes ,  Margaret Rose Ciafardini Kirkland ,  Kristine Anna Dougherty ,  Deepu John ,  David Kriegman ,  Vipanj B. Patel

IPC分类号： G09B19/00

CPC分类号： G09B19/00 ,  G06Q30/02 ,  G09B5/02

摘要： A system and method for providing a personalized face chart. A digital image of the subject's face is obtained. A facial region of the digital image is identified. A line drawing is generated based on at least the facial region of the digital image.

摘要翻译： 一种用于提供个性化脸部图表的系统和方法。 获得受试者脸部的数字图像。 识别数字图像的面部区域。 至少基于数字图像的面部区域生成线条图。

公开(公告)号：US20130210411A1

公开(公告)日：2013-08-15

申请号：US13586060

申请日：2012-08-15

申请人： ANUJ OJHA ,  ISAN A DOSHI ,  DEEPU JOHN ,  BRIAN M. GEORGE ,  SUDARSAN KRISHNAN ,  BENJAMIN A. CHEADLE

发明人： ANUJ OJHA ,  ISAN A DOSHI ,  DEEPU JOHN ,  BRIAN M. GEORGE ,  SUDARSAN KRISHNAN ,  BENJAMIN A. CHEADLE

IPC分类号： H04W8/24

CPC分类号： H04W8/245 ,  H04B17/21 ,  H04W24/00

摘要： A method includes receiving, at a device to be calibrated, a data packet from a second device that is directing the calibration. The data packet includes at least two segments, where each segment corresponds to at least one calibration instruction. The method includes conducting a calibration of the device according to the calibration instructions corresponding to the at least two segments.

摘要翻译： 一种方法包括在待校准的设备处接收来自正在指示校准的第二设备的数据分组。 数据包包括至少两个段，其中每个段对应于至少一个校准指令。 该方法包括根据对应于该至少两个段的校准指令进行设备的校准。

公开(公告)号：US07756085B2

公开(公告)日：2010-07-13

申请号：US10160874

申请日：2002-05-31

申请人： Daisuke Terasawa ,  Deepu John ,  Hao Liu ,  Qiuzhen (Joe) Zou ,  Sivarama Krishnan Venkatesan

发明人： Daisuke Terasawa ,  Deepu John ,  Hao Liu ,  Qiuzhen (Joe) Zou ,  Sivarama Krishnan Venkatesan

IPC分类号： H04B7/216

CPC分类号： H04B1/70735 ,  H04B2201/70707 ,  H04B2201/7071

摘要： Techniques for efficient searching in asynchronous systems, such as W-CDMA, as well as multi-mode searching, are disclosed. In one aspect, step one and step three search are performed in a single search engine. In another aspect, a search engine is configurable to search the offsets of a slot in step one search, producing sequential hypothesis energies, and peak detecting and sorting those energies. In yet another aspect, the peak detector and sorter are configurable to perform step one searching or step three/multimode searching. Various other aspects of the invention are also presented. These aspects have the benefit of circuit area and search-time efficiency which translate into reduced costs, increased standby time, increased acquisition speed, higher quality signal transmission, increased data throughput, decreased power, and improved overall system capacity.

摘要翻译： 公开了用于在诸如W-CDMA的异步系统中进行有效搜索的技术以及多模式搜索。 在一个方面，在单个搜索引擎中执行步骤1和步骤3搜索。 在另一方面，搜索引擎可配置为在步骤一搜索中搜索时隙的偏移量，产生顺序假设能量，以及峰值检测和排序这些能量。 在另一方面，峰值检测器和分类器可配置为执行步骤一搜索或步骤三/多模式搜索。 还提出了本发明的各种其它方面。 这些方面具有电路面积和搜索时间效率的优点，从而降低了成本，增加了待机时间，提高了采集速度，提高了信号传输质量，提高了数据吞吐量，降低了功耗，提高了整体系统容量。

公开(公告)号：US20090234716A1

公开(公告)日：2009-09-17

申请号：US12406063

申请日：2009-03-17

申请人： Satya Mallick ,  Kevin Barnes ,  Vipanj Patel ,  Deepu John ,  David Kriegman

发明人： Satya Mallick ,  Kevin Barnes ,  Vipanj Patel ,  Deepu John ,  David Kriegman

IPC分类号： G06Q30/00 ,  G06Q99/00

CPC分类号： G09G5/14 ,  G06F3/0482 ,  G06F3/04883 ,  G06Q30/0256 ,  G06Q30/0269 ,  G06Q30/0275 ,  G06Q30/0601 ,  G06Q40/04 ,  G09G5/06 ,  G09G2320/0666 ,  G09G2340/0407 ,  G09G2340/10 ,  G16H30/40

摘要： One or more embodiments of the program are directed to a plurality of methods for monetizing online personalized beauty product selections utilizing a technology for content-targeted Internet advertising on a virtual makeover website. Methods comprise: (1) categorizing facial features to select product advertisements for co-branding in a product palette; (2) an auction for webpage advertisement placements related to a user's facial features; (3) transforming a makeover “look” to advertise alternative products to produce the new look under different lighting conditions; (4) a gifting system to allow sale and gifting of products used to produce a makeover, where the makeover image may be packaged with the selected products in a gift package; and (5) recapturing users who would cancel a sale with an offer of less expensive comparable products.

摘要翻译： 程序的一个或多个实施例涉及多种利用在虚拟化妆网站上进行面向内容的互联网广告的技术来在线个性化美容产品选择获利的方法。 方法包括：（1）对面部特征进行分类，在产品调色板中选择产品广告进行联合品牌化; （2）与用户的面部特征相关的网页广告展示的拍卖; （3）在不同的照明条件下，改造“外观”来宣传替代产品以产生新的外观; （4）赠送系统，用于出售和赠送用于生产改造的产品，其中可以将礼品包装中的所选产品包装在一起; （5）重新招收使用较便宜的可比产品的报价取消销售的用户。

公开(公告)号：US06615341B2

公开(公告)日：2003-09-02

申请号：US09876189

申请日：2001-06-05

申请人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

发明人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

公开(公告)号：US06425070B1

公开(公告)日：2002-07-23

申请号：US09044086

申请日：1998-03-18

申请人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

发明人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

摘要翻译： 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。 此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。 因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。 当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。